公开(公告)号：US20230313365A1

公开(公告)日：2023-10-05

申请号：US18332638

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Kyung-Eun BYUN ,  Hyoungsub KIM ,  Taejin PARK ,  Hyeonjin SHIN ,  Hoijoon KIM ,  Wonsik AHN ,  Mirine LEEM

IPC: C23C16/30 ,  B22F7/00 ,  C23C16/46 ,  C23C16/448 ,  C23C16/455 ,  H01L21/02 ,  H01L21/285 ,  H01L31/032

CPC classification number: C23C16/305 ,  B22F7/008 ,  C23C16/46 ,  C23C16/448 ,  C23C16/45502 ,  C23C16/45514 ,  H01L21/02568 ,  H01L21/02581 ,  H01L21/28568 ,  H01L31/0324 ,  B22F2207/01 ,  B22F2302/45

Abstract: Provided are a metal chalcogenide thin film and a method and device for manufacturing the same. The metal chalcogenide thin film includes a transition metal element and a chalcogen element, and at least one of the transition metal element and the chalcogen element having a composition gradient along the surface of the metal chalcogenide thin film, the composition gradient being an in-plane composition gradient. The metal chalcogenide thin film may be prepared by using a manufacturing method including providing a transition metal precursor and a chalcogen precursor on a substrate by using a confined reaction space in such a manner that at least one of the transition metal precursor and the chalcogen precursor forms a concentration gradient according to a position on the surface of the substrate; and heat-treating the substrate.

公开(公告)号：US20230114347A1

公开(公告)日：2023-04-13

申请号：US18063909

申请日：2022-12-09

Applicant: Samsung Electronics Co., Ltd. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Changhyun KIM ,  Sang-Woo Kim ,  Kyung-Eun BYUN ,  Hyeonjin SHIN ,  Ahrum SOHN ,  Jaehwan JUNG

IPC: H01L21/02

Abstract: Disclosed herein are a method of forming a transition metal dichalcogenide thin film and a method of manufacturing a device including the same. The method of forming a transition metal dichalcogenide thin film includes: providing a substrate in a reaction chamber; depositing a transition metal dichalcogenide thin film on the substrate using a sputtering process that uses a transition metal precursor and a chalcogen precursor and is performed at a first temperature; and injecting the chalcogen precursor in a gas state and heat-treating the transition metal dichalcogenide thin film at a second temperature that is higher than the first temperature. The substrate may include a sapphire substrate, a silicon oxide (SiO2) substrate, a nanocrystalline graphene substrate, or a molybdenum disulfide (MoS2) substrate.

公开(公告)号：US20230079680A1

公开(公告)日：2023-03-16

申请号：US17829679

申请日：2022-06-01

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Keunwook SHIN ,  Kibum KIM ,  Kyung-Eun BYUN ,  Hyeonjin SHIN ,  Minhyun LEE ,  Changseok LEE

IPC: C01B32/186 ,  C01B32/188 ,  H01L29/41 ,  H01L29/40

Abstract: Provided are a wiring including a graphene layer and a method of manufacturing the wiring. The method may include growing a graphene layer on a substrate and doping the graphene layer with a metal. The graphene layer may be grown using a plasma of a hydrocarbon at a temperature of about 200° C. to about 600° C. by plasma enhanced chemical vapor deposition (PECVD).

公开(公告)号：US20230072863A1

公开(公告)日：2023-03-09

申请号：US17939303

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyu LEE ,  Sangwon KIM ,  Kyung-Eun BYUN ,  Yeonchoo CHO

IPC: H01L27/108

Abstract: A semiconductor element may include a substrate including source and drain regions formed in the substrate apart from each other by a trench, a gate insulating layer covering a bottom surface and a sidewall of the trench, a gate electrode including lower and upper buried portions. The lower buried portion may be in the trench with the gate insulating layer therearound and fill a lower region of the trench. The upper buried portion may be on the lower buried portion with the gate insulating layer therearound and fill an upper region of the trench. The upper buried portion may include a two-dimensional material layer in the trench on an upper surface of the first conductive layer and an upper region of the sidewall of the gate insulating layer, and a second conductive layer in the upper region of the trench and surrounded by the two-dimensional material layer.

公开(公告)号：US20220406911A1

公开(公告)日：2022-12-22

申请号：US17545373

申请日：2021-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minseok YOO ,  Minsu SEOL ,  Junyoung KWON ,  Kyung-Eun BYUN ,  Hyeonjin SHIN ,  Van Luan NGUYEN

IPC: H01L29/423 ,  H01L29/43

Abstract: Disclosed are an electronic device including a two-dimensional material, and a method of fabricating the electronic device. The electronic device may include a first metal layer including a transition metal, a second metal layer on the first metal layer and including gold (Au), and a two-dimensional material layer between the first metal layer and the second metal layer. The two-dimensional material layer may include a transition metal dichalcogenide (TMD). The two-dimensional material layer may be formed as a chalcogen element diffuses into the second metal layer and reacts with the transition metal of the first metal layer adjacent to the second metal layer.

公开(公告)号：US20220316052A1

公开(公告)日：2022-10-06

申请号：US17711147

申请日：2022-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwon KIM ,  Kyung-Eun BYUN ,  Yeonchoo CHO ,  Keunwook SHIN ,  Eunkyu LEE ,  Changseok LEE ,  Hyunjae SONG ,  Hyeonjin SHIN ,  Jungsoo YOON ,  Soyoung LEE ,  Hyunseok LIM

IPC: C23C16/26 ,  H01L29/45 ,  H01L21/285 ,  C23C16/511 ,  C23C16/505 ,  C23C16/02

Abstract: Provided are nanocrystalline graphene and a method of forming the same. The nanocrystalline graphene may include a plurality of grains formed by stacking a plurality of graphene sheets and has a grain density of about 500 ea/μm2 or higher and a root-mean-square (RMS) roughness in a range of about 0.1 or more to about 1.0 or less. When the nanocrystalline graphene has a grain density and a RMS roughness with these ranges, nanocrystalline graphene capable of covering the entirety of a large area on a substrate as a thin layer may be provided.

公开(公告)号：US20220254643A1

公开(公告)日：2022-08-11

申请号：US17547626

申请日：2021-12-10

Applicant: Samsung Electronics Co., Ltd. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Kyung-Eun BYUN ,  Sangwoo KIM ,  Minsu SEOL ,  Hyeonjin SHIN ,  Minseok SHIN ,  Pin ZHAO ,  Taehyeong KIM ,  Jaehwan JUNG

IPC: H01L21/308 ,  H01J37/34

Abstract: A method of forming a material film includes providing a non-photosensitive mask on a substrate to expose a partial region of the substrate, forming a material film on the partial region of the substrate using a sputtering process, removing the non-photosensitive mask, and heat-treating the substrate and the material film from which the non-photosensitive mask is removed under a first gas atmosphere. The material film includes a transition metal and a chalcogen element. The sputtering process may include an RF magnetron sputtering process. The heat treatment may be performed at a higher temperature than a temperature of the forming the material film.

公开(公告)号：US20220173221A1

公开(公告)日：2022-06-02

申请号：US17398363

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjin SHIN ,  Sangwon KIM ,  Kyung-Eun BYUN ,  Hyunjae SONG ,  Keunwook SHIN ,  Eunkyu LEE ,  Changseok LEE ,  Yeonchoo CHO ,  Taejin CHOI

IPC: H01L29/45 ,  H01L27/108 ,  H01L29/15 ,  H01L29/40

Abstract: An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of a peripheral region of the semiconductor layer, a metal layer facing the semiconductor layer, a graphene layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the graphene layer and the semiconductor and covering the first region.

公开(公告)号：US20210372786A1

公开(公告)日：2021-12-02

申请号：US17145966

申请日：2021-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyu LEE ,  Yeonchoo CHO ,  Sangwon KIM ,  Kyung-Eun BYUN ,  Hyunjae SONG ,  Hyeonjin SHIN

IPC: G01B15/02 ,  H01L21/66 ,  H01L21/285 ,  H01L29/45 ,  G01N23/2208

Abstract: A method of calculating a thickness of a graphene layer and a method of measuring a content of silicon carbide, by using X-ray photoelectron spectroscopy (XPS), are provided. The method of calculating the thickness of the graphene layer, which is directly grown on a silicon substrate, includes measuring the thickness of the graphene layer directly grown on the silicon substrate, by using a ratio between a signal intensity of a photoelectron beam emitted from the graphene layer and a signal intensity of a photoelectron beam emitted from the silicon substrate.

公开(公告)号：US20210355582A1

公开(公告)日：2021-11-18

申请号：US17318238

申请日：2021-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjin SHIN ,  Sangwon KIM ,  Kyung-Eun BYUN ,  Eunkyu LEE ,  Changhyun KIM ,  Changseok LEE

IPC: C23C16/50 ,  C23C16/26 ,  C23C16/32 ,  C01B32/182 ,  C01B21/064 ,  C01B25/00

Abstract: Provided are a conductive structure and a method of controlling a work function of metal. The conductive structure includes a conductive material layer including metal and a work function control layer for controlling a work function of the conductive structure by being bonded to the conductive material layer. The work function control layer includes a two-dimensional material with a defect.