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    Semiconductor memory device, method of testing the same and test system
    44.
    发明授权
    Semiconductor memory device, method of testing the same and test system 有权

    公开(公告)号：US11501846B2

    公开(公告)日：2022-11-15

    申请号：US17239651

    申请日：2021-04-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sanglok Kim ,  Youngdon Choi

    IPC: G11C29/56

    Abstract: A semiconductor memory device included in each of a plurality of chips which are divided by a scribe lane and formed on an upper surface of a wafer, includes a memory core and a built-in self test (BIST) circuit. The memory core includes a memory cell array that stores data and a data input/output circuit connected to a data input/output pad. The BIST circuit is connected to a test pad that is separate from the data input/output pad. The BIST circuit generates test pattern data including first parallel bits based on commands and addresses received from an external automatic test equipment (ATE) during a wafer level test process performed on the semiconductor memory device. The BIST circuit tests the memory core by applying the test pattern data to the memory cell array through the data input/output circuit.

    QUADRATURE ERROR CORRECTION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    45.
    发明申请
    QUADRATURE ERROR CORRECTION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20220336004A1

    公开(公告)日：2022-10-20

    申请号：US17508598

    申请日：2021-10-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hojun Yoon ,  Wonjoo Jung ,  Jaewoo Park ,  Youngchul Cho ,  Youngdon Choi ,  Junghwan Choi

    IPC: G11C11/4076 ,  H01L25/065

    Abstract: A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.

    Memory device supporting a high-efficient input/output interface and a memory system including the memory device
    46.
    发明授权
    Memory device supporting a high-efficient input/output interface and a memory system including the memory device 有权

    公开(公告)号：US11461251B2

    公开(公告)日：2022-10-04

    申请号：US17326513

    申请日：2021-05-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyungmin Jin ,  Jindo Byun ,  Younghoon Son ,  Youngdon Choi ,  Junghwan Choi

    IPC: G06F13/16 ,  H04L25/49

    Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.

    ANALOG-TO-DIGITAL CONVERSION
    49.
    发明申请
    ANALOG-TO-DIGITAL CONVERSION 有权

    公开(公告)号：US20250038754A1

    公开(公告)日：2025-01-30

    申请号：US18658820

    申请日：2024-05-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaeha Kim ,  Young Choi ,  Myoungbo Kwak ,  Jaewoo Park ,  Youngdon Choi ,  Junghwan Choi

    IPC: H03M1/06

    Abstract: The present disclosure relates to successive approximation register analog-to-digital converters. An example successive approximation register analog-to-digital converter includes a first sampling and holding circuit that samples an analog signal at a first point in time and generates a first input voltage, a second sampling and holding circuit that samples the analog signal at a second point in time and generates a second input voltage, and a first analog-to-digital converter. The first analog-to-digital converter performs a feed forward equalization function by receiving the first input voltage and the second input voltage, sampling the first input voltage and the second input voltage, and outputting a multi-bit digital signal based on a sampling result of the first input voltage and a sampling result of the second input voltage.

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