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公开(公告)号：US09123640B2
公开(公告)日：2015-09-01
申请号：US13892675
申请日：2013-05-13
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Antoine Khoueir , YoungPil Kim , Rodney Virgil Bowman
CPC classification number: H01L27/2481 , H01L27/2472 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147
Abstract: A memory device includes a stack of layers comprising a plurality of alternating layers of continuous electrically conductive material word line layers with layers of continuous electrically insulating material. A plurality of vias vertically extend through the stack of layers and a vertical bit line is disposed within each via. A layer of switching material separates the vertical bit line from the stack of layers, thereby forming an array of RRAM cells.
Abstract translation: 存储器件包括一叠层，包括具有连续电绝缘材料层的连续导电材料字线层的多个交替层。 多个通孔垂直延伸穿过堆叠层，并且垂直位线设置在每个通孔内。 开关材料层将垂直位线与层叠层隔开，从而形成RRAM单元阵列。
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公开(公告)号：US09064563B2
公开(公告)日：2015-06-23
申请号：US13762913
申请日：2013-02-08
Applicant: Seagate Technology LLC
Inventor： Antoine Khoueir , Mark Allen Gaertner , Ryan James Goss
CPC classification number: G11C13/0004 , G11C13/0002 , G11C13/0007 , G11C13/0011 , G11C13/0033 , G11C13/0035 , G11C13/0069
Abstract: A data storage device may generally be constructed and operated with at least one variable resistance memory cell configured with non-factory operational parameters by a controller. The non-factory operational parameters are assigned in response to an identified variance from a predetermined threshold in at least one variable resistance memory cell.
Abstract translation: 一般来说，数据存储装置可由至少一个由控制器配置有非工厂操作参数的可变电阻存储单元构成和操作。 响应于在至少一个可变电阻存储器单元中从预定阈值识别的方差来分配非出厂操作参数。
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43.发明授权Hash functions used to track variance parameters of resistance-based memory elements 有权哈希函数用于跟踪基于电阻的存储器元件的方差参数公开(公告)号：US09058870B2
公开(公告)日：2015-06-16
申请号：US13762979
申请日：2013-02-08
Applicant: Seagate Technology LLC
Inventor： David Scott Ebsen , Antoine Khoueir , Mark Allen Gaertner
CPC classification number: G11C13/0002 , G06F17/30949 , G11C13/0033 , G11C13/0035 , G11C13/004
Abstract: Parameters indicative of resistance variance of the memory elements are tracked. The resistance variance affects values of data stored in the resistance-based memory elements. A hash function is performed for each memory element. The hash function returns a reference to one of a plurality of counter elements. A value of each counter element is modified in response to the tracked parameter data of the associated memory element. Read operations affecting the memory elements are adjusted based on the values for the associated counter elements.
Abstract translation: 跟踪表示存储元件的电阻变化的参数。 电阻变化影响存储在基于电阻的存储元件中的数据的值。 对每个存储元件执行散列函数。 散列函数返回对多个计数元素之一的引用。 响应于相关联的存储器元件的跟踪参数数据修改每个计数器元件的值。 基于相关计数器元件的值来调整影响存储元件的读取操作。
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公开(公告)号：US20140244946A1
公开(公告)日：2014-08-28
申请号：US13777137
申请日：2013-02-26
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Antoine Khoueir , Jon D. Trantham , Kevin Gomez , Ara Patapoutian
IPC: G06F12/00
CPC classification number: G06F12/00 , G06F12/0238
Abstract: A plurality of addressable memory tiles each comprise one or more cross-point arrays. Each array comprises a plurality of non-volatile resistance-change memory cells. A controller is configured to couple to the array and to a host system. The controller is configured to perform receiving, from the host system, one or more data objects each having a size equal to a predetermined logical block size, and storing the one or more data objects in a corresponding integer number of one or more of the memory tiles.
Abstract translation: 多个可寻址存储器块各自包括一个或多个交叉点阵列。 每个阵列包括多个非易失性电阻变化存储单元。 控制器被配置为耦合到阵列和主机系统。 控制器被配置为执行从主机系统接收每个具有等于预定逻辑块大小的大小的一个或多个数据对象，并且将一个或多个数据对象存储在相应整数个存储器中的一个或多个存储器中 瓷砖。
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45.发明申请Fast Power Loss Recovery By Swapping Boot and Recovery Data Sets in a Memory 审中-公开通过交换内存中的引导和恢复数据集快速断电恢复公开(公告)号：US20140241071A1
公开(公告)日：2014-08-28
申请号：US13777844
申请日：2013-02-26
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Ryan James Goss , David Scott Ebsen , Antoine Khoueir
IPC: G11C7/10
CPC classification number: G11C7/20
Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, a recovery data set representing a current state of a storage device is stored in a rewritable non-volatile memory responsive to detection of a potentially imminent deactivation of the device. The recovery data set is swapped with a boot data set in said memory responsive to subsequent deactivation of the device. The boot data set is subsequently used to transition the device from a deactivated mode to an operationally ready mode during device reinitialization. The boot data set is thereafter swapped with the recovery data set to return the device to the current state.
Abstract translation: 用于管理存储器中的数据的方法和装置。 根据一些实施例，响应于检测到设备的潜在即将停用而将表示存储设备的当前状态的恢复数据集存储在可重写非易失性存储器中。 所述恢复数据集与所述存储器中的引导数据集交换，以响应于所述设备的随后的去激活。 引导数据集随后用于在设备重新初始化期间将设备从停用模式转换到操作就绪模式。 此后，引导数据集与恢复数据集交换，以使设备返回到当前状态。
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Patent Agency Ranking
46.发明申请METHODS AND APPARATUSES USING A TRANSFER FUNCTION TO PREDICT RESISTANCE SHIFTS AND/OR NOISE OF RESISTANCE-BASED MEMORY 有权使用转移函数预测电阻变化和/或基于电阻的存储器的噪声的方法和装置公开(公告)号：US20140241032A1
公开(公告)日：2014-08-28
申请号：US13776886
申请日：2013-02-26
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Ara Patapoutian , Ryan James Goss , Antoine Khoueir
CPC classification number: G11C13/0002 , G11C7/04 , G11C11/56 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C13/0035 , G11C13/004 , G11C13/0069 , G11C29/08 , G11C2013/0076
Abstract: Two or more workload indicators affecting a memory cell of a resistance-based, non-volatile memory are measured. The two or more workload indicators are applied to a transfer function that predicts a resistance shift and/or resistance noise variance in response to the two or more workload indicators. A result of the transfer function is applied to shift and/or determine a threshold resistance used for at least one of a program operation and a read operation affecting the memory cell. An error rate of the memory cell is reduced as a result.
Abstract translation: 测量影响基于电阻的非易失性存储器的存储单元的两个或多个工作负载指示器。 两个或多个工作负载指示符被应用于响应于两个或更多个工作负载指示器预测电阻偏移和/或电阻噪声方差的传递函数。 应用传递函数的结果来移位和/或确定用于影响存储器单元的程序操作和读取操作中的至少一个的阈值电阻。 结果，存储单元的错误率降低。
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47.发明申请APPLYING A BIAS SIGNAL TO MEMORY CELLS TO REVERSE A RESISTANCE SHIFT OF THE MEMORY CELLS 有权对存储细胞应用偏置信号以反转记忆细胞的电阻移位公开(公告)号：US20140219001A1
公开(公告)日：2014-08-07
申请号：US13761301
申请日：2013-02-07
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Ara Patapoutian , Antoine Khoueir , Ryan James Goss , Jon D. Trantham
IPC: G11C13/00
CPC classification number: G11C13/0002 , G11C11/5614 , G11C11/5678 , G11C13/0004 , G11C13/0011 , G11C13/0033
Abstract: Data is written to cells of a resistance-based, non-volatile memory. An activity metric is tracked since the writing of the data to the cells. In response to the activity metric satisfying a threshold, a bias signal is applied to the cells to reverse a resistance shift of the cells.
Abstract translation: 数据被写入基于电阻的非易失性存储器的单元。 自从将数据写入单元格后，会跟踪活动度量。 响应于满足阈值的活动度量，将偏置信号施加到单元以反转单元的电阻偏移。
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公开(公告)号：US11175980B2
公开(公告)日：2021-11-16
申请号：US16729206
申请日：2019-12-27
Applicant: Seagate Technology LLC
Inventor： Mehmet Emin Aklik , Antoine Khoueir , Darshana H. Mehta , Nicholas Lien
Abstract: Read error mitigation in solid-state memory devices. A solid-state drive (SSD) includes a read error mitigation module that monitors one or more memory regions. In response to detecting uncorrectable read errors, memory regions of the memory device may be identified and preemptively retired. Example approaches include identifying a memory region as being suspect such that upon repeated read failures within the memory region, the memory region is retired. Moreover, memory regions may be compared to peer memory regions to determine when to retire a memory region. The read error mitigation module may trigger a test procedure on a memory region to detect the susceptibility of a memory region to read error failures. By detecting read error failures and retirement of a memory region, data loss and/or data recovery processes may be limited to improve drive performance and reliability.
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公开(公告)号：US20210133025A1
公开(公告)日：2021-05-06
申请号：US16670329
申请日：2019-10-31
Applicant: Seagate Technology LLC
Inventor： Mehmet Emin Aklik , Antoine Khoueir , Ara Patapoutian , Colin Hill , Kurt Walter Getreuer , Darshana H. Mehta
Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, flash memory cells are arranged along word lines to which read voltages are applied to sense programmed states of the memory cells, with the flash memory cells along each word line being configured to concurrently store multiple pages of data. An encoder circuit is configured to apply error correction encoding to input data to form code words having user data bits and code bits, where an integral number of the code words are written to each page. A reference voltage calibration circuit is configured to randomly select a single selected code word from each page and to use the code bits from the single selected code word to generate a set of calibrated read voltages for the associated page.
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公开(公告)号：US20210064249A1
公开(公告)日：2021-03-04
申请号：US16560858
申请日：2019-09-04
Applicant: Seagate Technology LLC
Inventor： Darshana H. Mehta , Antoine Khoueir
Abstract: Technologies are described herein for or extending the lifespan of a solid-state drive by using worn-out MLC flash blocks in SLC mode to extend their useful life. Upon identifying a first storage location in the storage media of an SSD as a candidate for defecting, the first storage location is switched from a first programming mode to a second programming mode, where the second programming mode results in a lower storage density of storage locations than the first programming mode. In conjunction with switching the first storage location to the first programming mode, a second storage location in the storage media is switched from the second programming mode to the first programming mode to ensure that the total capacity of the storage media remains at or above the rated capacity.
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