公开(公告)号：US06772321B2

公开(公告)日：2004-08-03

申请号：US09761360

申请日：2001-01-16

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F1500

CPC分类号： G06F9/3877 ,  G06F9/383 ,  G06F9/3842

摘要： One embodiment of the present invention provides a system that prefetches from memory by using an assist processor that performs data speculation and that executes in advance of a primary processor. The system operates by executing executable code on the primary processor while simultaneously executing a reduced version of the executable code on the assist processor. This allows the assist processor to generate the same pattern of memory references that the primary processor generates in advance of when the primary processor generates the memory references. While executing the reduced version of the executable code, the system predicts a data value returned by a long latency operation within the executable code. The system subsequently uses the predicted data value to continue executing the reduced version of the executable code without having to wait for the long latency operation to complete.

摘要翻译： 本发明的一个实施例提供一种通过使用执行数据推测并且在主处理器之前执行的辅助处理器来从存储器预取的系统。 该系统通过在主处理器上执行可执行代码同时在辅助处理器上执行可执行代码的简化版本来操作。 这允许辅助处理器在主处理器产生存储器引用之前产生与主处理器产生的相同的存储器引用模式。 在执行可执行代码的缩减版本的同时，系统预测在可执行代码内的长延迟操作返回的数据值。 系统随后使用预测数据值继续执行可执行代码的简化版本，而不必等待长延迟操作完成。

公开(公告)号：US06463526B1

公开(公告)日：2002-10-08

申请号：US09420335

申请日：1999-10-18

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F952

CPC分类号： G06F9/3851 ,  G06F8/45 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3863 ,  G06F9/3885 ,  G06F12/084 ,  G06F2212/507

摘要： One embodiment of the present invention provides a system that facilitates multi-dimensional space and time dimensional execution of computer programs. The system includes a head thread that executes program instructions and a series of speculative threads that execute program instructions in advance of the head thread, wherein each speculative thread executes program instructions in advance of preceding speculative threads in the series. The head thread accesses a primary version of the memory element and the series of speculative threads access space-time dimensioned versions of the memory element. The system starts by receiving a memory access to the memory element. If the memory access is a write operation by the head thread or a speculative thread, the system determines if a version of the memory element associated with the head thread or speculative thread exists. If not, the system creates a version of the memory element for the thread. Next, the system performs the write operation to the version of the memory element. After performing the write operation, the system checks status information associated with the memory element to determine if the memory element has been read by a following speculative thread in the series of speculative threads. If so, the system causes the following speculative thread and any successive speculative threads in the series to roll back so that the following speculative thread and any successive speculative threads in the series can read a result of the write operation. If not, the system performs the write operation to all successive space-time dimensioned versions of the memory element.

摘要翻译： 本发明的一个实施例提供一种促进计算机程序的多维空间和时间尺寸执行的系统。 该系统包括执行程序指令的头螺纹和在头部线程之前执行程序指令的一系列推测线程，其中每个推测线程在该系列中的先前推测线程之前执行程序指令。 头线程访问存储器元件的主要版本，并且一系列推测线程访问存储器元件的时空维度版本。 系统通过接收存储器元件的存储器访问来开始。 如果存储器访问是头部线程或推测线程的写入操作，则系统确定是否存在与头部线程或推测线程相关联的存储器元件的版本。 如果没有，系统会创建线程的内存元素的版本。 接下来，系统对存储元件的版本执行写入操作。 在执行写入操作之后，系统检查与存储器元件相关联的状态信息，以确定存储器元件是否已被一系列推测性线程中的以下推测线程读取。 如果是这样，系统会导致以下推测线程和系列中任何连续的推测线程回滚，以便以下推测线程和系列中任何连续的推测线程可以读取写操作的结果。 如果没有，则系统对所有连续的时空维度版本的存储器元件执行写入操作。

公开(公告)号：US06460067B1

公开(公告)日：2002-10-01

申请号：US09327399

申请日：1999-06-07

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F1500

CPC分类号： G06F9/52

摘要： One embodiment provides for a system that uses a time stamp in order to more efficiently mark objects to keep track of accesses to fields with the objects. Upon receiving a first reference to a first field in an object, the system determines whether the first field has been accessed within a current time period. The system does so by retrieving a time stamp associated with the object. This time stamp indicates the last time any marking bit associated with any field in the object was updated. The system compares the time stamp with a current time value associated with the current time period. The system additionally retrieves a first marking bit associated with the first field and determines if the first marking bit is set. If the first marking bit is set and if the time stamp equals the current time value, the system determines that the first field has been accessed in the current time period. The system indicates that a second field in the object has been accessed in the current time period upon receiving a second reference to the second field. In response to the second reference, the system sets a second marking bit associated with the second field. The system also updates the time stamp associated with the object, if necessary, so that the time stamp contains the current time value.

摘要翻译： 一个实施例提供了一种使用时间戳的系统，以便更有效地标记对象以跟踪对具有对象的字段的访问。 在接收到对象中的第一个字段的第一个引用后，系统确定在当前时间段内是否已经访问了第一个字段。 系统通过检索与对象相关联的时间戳来实现。 该时间戳表示最后一次与对象中的任何字段相关联的任何标记位被更新。 系统将时间戳与当前时间段相关联的当前时间值进行比较。 系统还检索与第一场相关联的第一标记位，并确定是否设置了第一标记位。 如果设置了第一个标记位，并且如果时间戳等于当前时间值，则系统确定在当前时间段内已经访问了第一个字段。 系统指示当接收到对第二字段的第二个引用时，当前时间段中已经访问了该对象中的第二个字段。 响应于第二参考，系统设置与第二场相关联的第二标记位。 如果需要，系统还更新与对象相关联的时间戳，以便时间戳包含当前时间值。

公开(公告)号：US06438677B1

公开(公告)日：2002-08-20

申请号：US09422028

申请日：1999-10-20

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F952

CPC分类号： G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863

摘要： One embodiment of the present invention provides a system that supports space and time dimensional program execution by facilitating accesses to different versions of a memory element. The system supports a head thread that executes program instructions and a speculative thread that executes program instructions in advance of the head thread. The head thread accesses a primary version of the memory element, and the speculative thread accesses a space-time dimensioned version of the memory element. During a reference to the memory element by the head thread, the system accesses the primary version of the memory element. During a reference to the memory element by the speculative thread, the speculative thread accesses a pointer associated with the primary version of the memory element, and accesses a version of the memory element through the pointer. Note that the pointer points to the space-time dimensioned version of the memory element if the space-time dimensioned version of the memory element exists. In one embodiment of the present invention, the pointer points to the primary version of the memory element if the space-time dimensioned version of the memory element does not exist.

摘要翻译： 本发明的一个实施例提供一种通过促进对存储器元件的不同版本的访问来支持空间和时间维度程序执行的系统。 该系统支持执行程序指令的头部线程和在头部线程之前执行程序指令的推测线程。 头线程访问存储器元件的主要版本，并且推测线程访问存储器元件的时空维度版本。 在通过头部线程引用存储器元件期间，系统访问存储器元件的主要版本。 在通过推测线程对存储器元件的引用期间，推测线程访问与存储器元件的主版本相关联的指针，并且通过指针访问存储器元件的版本。 请注意，如果内存元素的时空维度版本存在，则指针指向内存元素的时空维度版本。 在本发明的一个实施例中，如果存储元件的时空尺寸版本不存在，则指针指向存储元件的主版本。

公开(公告)号：US06353881B1

公开(公告)日：2002-03-05

申请号：US09313229

申请日：1999-05-17

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F952

CPC分类号： G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863

摘要： A system is provided that facilitates space and time dimensional execution of computer programs through selective versioning of memory elements located in a system heap. The system includes a head thread that executes program instructions and a speculative thread that simultaneously executes program instructions in advance of the head thread with respect to the time dimension of sequential execution of the program. The collapsing of the time dimensions is facilitated by expanding the heap into two space-time dimensions, a primary dimension (dimension zero), in which the head thread operates, and a space-time dimension (dimension one), in which the speculative thread operates. In general, each dimension contains its own version of an object and objects created by the thread operating in the dimension. The head thread generally accesses a primary version of a memory element and the speculative thread generally accesses a corresponding space-time dimensioned version of the memory element. During a write by the head thread, the system performs the write to all dimensions of the memory element. Note that if the dimensions are collapsed at this address a single update will update all time dimensions. It also checks status information associated with the memory element to determine if the memory element has been read by the speculative thread. If so, the system causes the speculative thread to roll back so that the speculative thread can read a result of the write operation.

摘要翻译： 提供了一种系统，其通过对位于系统堆中的存储器元件进行选择性版本化来促进计算机程序的空间和时间尺寸的执行。 该系统包括执行程序指令的头螺纹和相对于程序的顺序执行的时间维度在头部线程之前同时执行程序指令的推测线程。 通过将堆扩展到两个时空维度（头线程操作的主维度（维度零））和空时维度（维度一）来促进时间维度的崩溃，其中推测线程 操作。 通常，每个维度都包含自己的一个对象的版本，以及由维度中的线程创建的对象。 头部线程通常访问存储器元件的主要版本，并且推测线程通常访问存储器元件的对应的时空维度版本。 在头部线程的写入期间，系统对存储器元件的所有维进行写入。 请注意，如果维度在此地址中折叠，则单个更新将更新所有时间维。 它还检查与存储器元件相关联的状态信息以确定存储器元件是否已被推测性线程读取。 如果是这样，系统会使推测线程回滚，以便推测线程可以读取写入操作的结果。

公开(公告)号：US08447931B1

公开(公告)日：2013-05-21

申请号：US11173110

申请日：2005-07-01

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

IPC分类号： G06F12/00

CPC分类号： G06F9/30141 ,  G06F9/383 ,  G06F9/3867 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1075 ,  G11C8/08 ,  G11C2207/107 ,  G11C2207/108

摘要： One embodiment of the present invention provides a processor that supports multiple-issue execution. This processor includes a register file, which contains an array of memory cells, wherein the memory cells contain bits for architectural registers of the processor. The register file also includes multiple read ports and multiple write ports to support multiple-issue execution. During operation, if multiple read ports simultaneously read from a given register, the register file is configured to: read each bit of the given register out of the array of memory cells through a single bitline associated with the bit; and to use a driver located outside of the array of memory cells to drive the bit to the multiple read ports. In this way, each memory cell only has to drive a single bitline (instead of multiple bitlines) during a multiple-port read operation, thereby allowing memory cells to use smaller and more power-efficient drivers for read operations.

摘要翻译： 本发明的一个实施例提供一种支持多次执行的处理器。 该处理器包括一个寄存器文件，该寄存器文件包含一个存储单元阵列，其中存储单元包含处理器结构寄存器的位。 注册文件还包括多个读取端口和多个写入端口，以支持多次执行。 在操作期间，如果从给定寄存器同时读取多个读取端口，则寄存器文件被配置为：通过与该位相关联的单个位线，将给定寄存器的每个位从存储器单元阵列中读出; 并使用位于存储器单元阵列之外的驱动器将该位驱动到多个读取端口。 以这种方式，每个存储器单元仅在多端口读取操作期间仅驱动单个位线（而不是多个位线），从而允许存储器单元使用较小且更省电的驱动器进行读取操作。

公开(公告)号：US07930695B2

公开(公告)日：2011-04-19

申请号：US11418652

申请日：2006-05-05

申请人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

发明人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

IPC分类号： G06F9/46

CPC分类号： G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3857

摘要： One embodiment of the present invention provides a system that synchronizes threads on a multi-threaded processor. The system starts by executing instructions from a multi-threaded program using a first thread and a second thread. When the first thread reaches a predetermined location in the multi-threaded program, the first thread executes a Start-Transactional-Execution (STE) instruction to commence transactional execution, wherein the STE instruction specifies a location to branch to if transactional execution fails. During the subsequent transactional execution, the first thread accesses a mailbox location in memory (which is also accessible by the second thread) and then executes instructions that cause the first thread to wait. When the second thread reaches a second predetermined location in the multi-threaded program, the second thread signals the first thread by accessing the mailbox location, which causes the transactional execution of the first thread to fail, thereby causing the first thread to resume non-transactional execution from the location specified in the STE instruction. In this way, the second thread can signal to the first thread without the first thread having to poll a shared variable.

摘要翻译： 本发明的一个实施例提供了一种在多线程处理器上同步线程的系统。 系统通过使用第一个线程和第二个线程执行来自多线程程序的指令来启动。 当第一线程到达多线程程序中的预定位置时，第一线程执行开始 - 事务执行（STE）指令以开始事务执行，其中STE指令指定分支到事务执行失败的位置。 在随后的事务执行期间，第一个线程访问存储器中的邮箱位置（也可由第二个线程访问），然后执行使第一个线程等待的指令。 当第二线程到达多线程程序中的第二预定位置时，第二线程通过访问邮箱位置来发信号通知第一线程，这导致第一线程的事务性执行失败，从而使第一线程恢复为非线程， 从STE指令中指定的位置进行事务执行。 以这种方式，第二线程可以向第一线程发信号，而第一线程不必轮询共享变量。

公开(公告)号：US20100191993A1

公开(公告)日：2010-07-29

申请号：US12361422

申请日：2009-01-28

申请人： Shailender Chaudhry ,  Quinn A. Jacobson ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Quinn A. Jacobson ,  Marc Tremblay

IPC分类号： G06F1/32 ,  G06F1/26 ,  G06F9/30

CPC分类号： G06F9/3867 ,  G06F1/206 ,  G06F1/3203 ,  G06F9/3869 ,  Y02D10/16

摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.

摘要翻译： 处理器包括提供节流功率输出信号的装置。 节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。 处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。 在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不会物理地改变处理器周期或任何处理器供电电压。

公开(公告)号：US20100049957A1

公开(公告)日：2010-02-25

申请号：US12197629

申请日：2008-08-25

申请人： Marc Tremblay ,  Shailender Chaudhry

发明人： Marc Tremblay ,  Shailender Chaudhry

IPC分类号： G06F9/30

CPC分类号： G06F9/3889 ,  G06F9/3804 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

摘要： Embodiments of the present invention provide a system that executes program code in a processor. The system starts by executing the program code in a normal mode using a primary strand while concurrently executing the program code ahead of the primary strand using a subordinate strand in a scout mode. Upon resolving a branch using the subordinate strand, the system records a resolution for the branch in a speculative branch resolution table. Upon subsequently encountering the branch using the primary strand, the system uses the recorded resolution from the speculative branch resolution table to predict a resolution for the branch for the primary strand. Upon determining that the resolution of the branch was mispredicted for the primary strand, the system determines that the subordinate strand mispredicted the branch. The system then recovers the subordinate strand to the branch and restarts the subordinate strand executing the program code.

摘要翻译： 本发明的实施例提供一种在处理器中执行程序代码的系统。 系统通过使用主链在正常模式下执行程序代码，同时使用侦察模式中的从属线同时执行主链前面的程序代码来开始。 在使用下级线解析分支时，系统在推测分支分辨率表中记录分支的分辨率。 在随后使用主链遇到分支时，系统使用来自推测性分支分辨率表的记录分辨率来预测主股的分支的分辨率。 在确定分支的决议对于主要股份进行了错误估计时，系统确定下级股错误地预测了分行。 系统然后将下级线路恢复到分支，并重新启动执行程序代码的下级线程。

公开(公告)号：US07634641B2

公开(公告)日：2009-12-15

申请号：US11361257

申请日：2006-04-24

申请人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

发明人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

IPC分类号： G06F9/00 ,  G06F9/40

CPC分类号： G06F9/3851 ,  G06F9/383 ,  G06F9/3842 ,  G06F9/3863

摘要： One embodiment of the present invention provides a system which performs simultaneous speculative threading. The system staffs by executing instructions in normal execution mode using a first thread. Upon encountering a data-dependent stall condition, the first thread generates an architectural checkpoint and commences execution of instructions in execute-ahead mode. During execute-ahead mode, the first thread executes instructions that can be executed and defers instructions that cannot be executed into a deferred queue. When the data dependent stall condition has been resolved, the first thread generates a speculative checkpoint and continues execution in execute-ahead mode. At the same time, the second thread commences execution in a deferred mode. During execution in the deferred mode, the second thread executes instructions deferred by the first thread.

摘要翻译： 本发明的一个实施例提供一种执行同时投机线程的系统。 系统通过使用第一个线程在正常执行模式下执行指令来启动。 在遇到数据相关的停顿条件时，第一个线程生成架构检查点，并以执行提前模式开始执行指令。 在执行提前模式期间，第一个线程执行可执行的指令，并将不能执行的指令拖到延迟队列中。 当数据相关的停顿条件已经解决时，第一个线程生成一个推测性检查点，并以执行提前模式继续执行。 同时，第二个线程以延迟模式开始执行。 在延迟模式执行期间，第二线程执行由第一线程延迟的指令。