公开(公告)号：US20210013238A1

公开(公告)日：2021-01-14

申请号：US16919422

申请日：2020-07-02

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Yoshihito HARA ,  Tetsuo KIKUCHI ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Masamitsu YAMANAKA ,  Hitoshi TAKAHATA ,  Hajime IMAI ,  Tohru DAITOH

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368

Abstract: An active matrix substrate includes a substrate; a plurality of gate bus lines and a plurality of source bus lines; an oxide semiconductor TFT that includes an oxide semiconductor layer, a gate insulating layer, and a gate electrode; a pixel electrode; and an upper insulating layer. The oxide semiconductor layer includes a high resistance region, and a first region and a second region. The high resistance region includes a channel region, a first channel offset region, and a second channel offset region. The upper insulating layer is disposed so as to overlap the channel region, the first channel offset region, and the second channel offset region, and so as not to overlap any of the first region and the second region, when viewed from the normal direction of the main surface of the substrate.

公开(公告)号：US20200150472A1

公开(公告)日：2020-05-14

申请号：US16683726

申请日：2019-11-14

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Tohru DAITOH ,  Hajime IMAI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Kengo HARA ,  Masamitsu YAMANAKA ,  Hitoshi TAKAHATA

IPC: G02F1/1368 ,  G02F1/1362 ,  G02F1/1333

Abstract: A substrate includes thin film transistors, each of which includes: an upper gate electrode formed of a first conductive film and continuous with one of gate lines; a source electrode formed of a second conductive film and continuous with one of source lines; a channel region formed of a portion of a semiconductor film over which an upper gate insulating film is disposed and overlapping the upper gate electrode; a source region formed of a portion of the semiconductor film and continuous with the channel region, and a drain region formed of a portion of the semiconductor film and continuous with the channel region on an opposite side of the channel region from the source region. The source electrode connects the source line and the source region through a first contact hole in an interlayer insulating film disposed over the first conductive film and containing a photosensitive material.

公开(公告)号：US20200058678A1

公开(公告)日：2020-02-20

申请号：US16343024

申请日：2017-10-12

Applicant: Sharp Kabushiki Kaisha

Inventor： Teruyuki UEDA ,  Hideki KITAGAWA ,  Tohru DAITOH ,  Hajime IMAI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Tetsuo KIKUCHI ,  Toshikatsu ITOH ,  Kengo HARA

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/49 ,  H01L27/02 ,  G02F1/1368 ,  G02F1/1362

Abstract: Provided is an active matrix substrate (100A) including: a gate metal layer (15) that has a two-layer structure composed of a Cu layer (15b) and a Ti layer (15a); a first insulating layer (16) on the gate metal layer (15); a source metal layer (18) that is formed on the first insulating layer (16) and has a two-layer structure composed of a Cu layer (18b) and a Ti layer (18a); a second insulating layer (19) on the source metal layer (18); a conductive layer (25) that is formed on the second insulating layer (19), and is in contact with the gate metal layer (15) within a first opening (16a1) formed in the first insulating layer (16) and is in contact with the source metal layer (18) within a second opening (19a2) formed in the second insulating layer (19); and a first transparent conductive layer (21) that is formed on the conductive layer (25) and includes any of a pixel electrode, a common electrode and an auxiliary capacitor electrode. The conductive layer (25) does not include any of the pixel electrode, the common electrode, and the auxiliary capacitor electrode, and does not have a Ti layer being in contact with the Cu layer (15b) of the gate metal layer (15).

公开(公告)号：US20190333461A1

公开(公告)日：2019-10-31

申请号：US16309958

申请日：2017-08-04

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Hajime IMAI ,  Takashi TERAUCHI ,  Shinya OHIRA ,  Isao OGASAWARA ,  Satoshi HORIUCHI

IPC: G09G3/36 ,  H01L27/12 ,  G02F1/1362

Abstract: An active-matrix substrate according to an embodiment of the present invention includes a plurality of first TFTs that are arranged within a display area, an inorganic insulating layer that covers the plurality of first TFTs, an organic insulating layer that is provided on the inorganic insulating layer, a plurality of second TFTs that are arranged within a non-display area, and a source and gate metal connection portion that is positioned within the non-display area, a first conductive layer that is formed from an identical conductive film with a gate wiring line and a second conductive layer that is formed from an identical conductive film with a source wiring line being connected to each other at the source and gate metal connection portion. Each of the plurality of first TFTs is an oxide semiconductor TFT. At least one second TFT among the plurality of second TFTs is covered with the organic insulating layer. The source and gate metal connection portion is not covered with the organic insulating layer.

公开(公告)号：US20190280126A1

公开(公告)日：2019-09-12

申请号：US16293900

申请日：2019-03-06

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Masamitsu YAMANAKA ,  Tohru DAITOH ,  Hajime IMAI ,  Kengo HARA

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  G02F1/1368

Abstract: A semiconductor device includes a thin film transistor, wherein: a semiconductor layer of the thin film transistor has a layered structure including a lower oxide semiconductor layer including In, Ga, Zn and Sn and an upper oxide semiconductor layer arranged on the lower oxide semiconductor layer and including In, Ga and Zn; a thickness of the lower oxide semiconductor layer is 20 nm or less; an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer is 5% or more; the upper oxide semiconductor layer includes no Sn, or an atomic ratio of Sn with respect to all metal elements of the upper oxide semiconductor layer is smaller than an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer; and a first angle θ1 between a side surface and a lower surface of the lower oxide semiconductor layer is smaller than a second angle θ2 between a side surface and a lower surface of the upper oxide semiconductor layer.

公开(公告)号：US20180277574A1

公开(公告)日：2018-09-27

申请号：US15775026

申请日：2017-01-26

Applicant: Sharp Kabushiki Kaisha

Inventor： Hisao OCHI ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo FUJITA ,  Hideki KITAGAWA ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Teruyuki UEDA

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/45 ,  H01L29/24 ,  H01L29/66 ,  H01L21/02 ,  H01L21/441

CPC classification number: H01L27/1225 ,  G02F1/13454 ,  G02F1/13624 ,  G02F1/1368 ,  G02F2202/10 ,  H01L21/02472 ,  H01L21/02483 ,  H01L21/02505 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/441 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/1251 ,  H01L27/1262 ,  H01L27/127 ,  H01L29/24 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/7869 ,  H01L29/78696

Abstract: An active matrix substrate includes a first TFT (10), a second TFT (20) disposed per pixel, and a circuit including the first TFT. The first and second TFTs each include a gate electrode (102A, 102B), a gate insulating layer (103), an oxide semiconductor layer (104A, 104B), and source and drain electrodes in contact with an upper surface of the oxide semiconductor layer. The oxide semiconductor layer (104A, 104B) has a stacked structure including a first semiconductor layer (104e, 104c) in contact with the source and drain electrodes and a second semiconductor layer that is disposed on a substrate-side of the first semiconductor layer and that has a smaller energy gap than the first semiconductor layer. The oxide semiconductor layers (104A) and (104B) are different from each other in terms of the composition and/or the number of stacked layers. The first TFT has a larger threshold voltage than the second TFT.

公开(公告)号：US20170090229A1

公开(公告)日：2017-03-30

申请号：US15316091

申请日：2015-05-29

Applicant: Sharp Kabushiki Kaisha

Inventor： Hajime IMAI ,  Tohru DAITOH ,  Hisao OCHI ,  Tetsuo FUJITA ,  Hideki KITAGAWA ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Shingo KAWASHIMA

IPC: G02F1/1368 ,  G02F1/1362 ,  G02F1/1333

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136295 ,  G02F2001/13685 ,  G02F2201/123 ,  G02F2202/10 ,  H01L27/1225 ,  H01L29/78633 ,  H01L29/78648 ,  H01L29/7869

Abstract: The semiconductor device of the present invention is provided with: source wiring lines that are formed on a substrate; light-shielding members that are in the same layer as the source wiring lines; a source insulating film that covers the source wiring lines and the like; holes that penetrate the source insulating film; channel region that are formed of an oxide semiconductor film that is formed on the source insulating film so as to overlap the light-shielding members; source electrode portions that are formed of the oxide semiconductor film, the resistance of which has been decreased, and that are connected to the source wiring lines via the holes; drain electrode portions that are formed of the oxide semiconductor film, the resistance of which has been decreased, and that oppose the source electrode portions with the channel region being interposed therebetween; gate insulating films that are formed on the channel region; and gate electrodes that are formed on the gate insulating films so as to overlap the channel region.