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    System and method for controlling manufacturing processes, and method for manufacturing a semiconductor device
    42.
    发明申请
    System and method for controlling manufacturing processes, and method for manufacturing a semiconductor device 失效
    用于控制制造工艺的系统和方法，以及制造半导体器件的方法

    公开(公告)号：US20050233601A1

    公开(公告)日：2005-10-20

    申请号：US11086220

    申请日：2005-03-23

    申请人： Norihiko Tsuchiya ,  Yukihiro Ushiku

    发明人： Norihiko Tsuchiya ,  Yukihiro Ushiku

    IPC分类号： H01L27/108 ,  H01L21/00 ,  H01L21/02 ,  H01L21/66 ,  H01L21/8242 ,  H01L21/8244 ,  H01L21/8247 ,  H01L27/11 ,  H01L27/115 ,  H01L29/78

    CPC分类号： H01L21/67253 ,  H01L22/20 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A control system for a manufacturing process includes an inspection tool inspecting a dislocation image in semiconductor substrate processed by manufacturing processes; an inspection information input module configured to acquire the inspected dislocation image; a process condition input module acquiring process conditions of the manufacturing processes; a structure information input module acquiring structure of the semiconductor substrate processed by target manufacturing process; a stress analysis module calculating stresses at nodes provided in the structure, based on target process condition and the structure; an origin setting module providing origins at positions where stress concentration having stress value not less than reference value is predicted; a dislocation dynamics analysis module calculating dislocation pattern in stress field for each position of the origins; and a dislocation pattern comparison module comparing the dislocation pattern with the inspected dislocation image so as to determine whether the target manufacturing process is critical manufacturing process.

    摘要翻译： 用于制造工艺的控制系统包括检查通过制造工艺处理的半导体衬底中的位错图像的检查工具; 检查信息输入模块，被配置为获取所检查的位错图像; 过程条件输入模块获取制造过程的处理条件; 通过目标制造工艺处理的半导体衬底的结构信息输入模块获取结构; 应力分析模块，根据目标过程条件和结构计算结构中提供的节点处的应力; 原点设定模块，其在具有应力值不小于参考值的应力集中的位置处提供起点; 位错动力学分析模块计算各个位置的应力场位错模式; 以及位错图案比较模块，将位错图案与被检查的位错图像进行比较，以确定目标制造过程是否是关键的制造过程。

    System and method for controlling manufacturing apparatuses
    43.
    发明申请
    System and method for controlling manufacturing apparatuses 失效
    用于控制制造装置的系统和方法

    公开(公告)号：US20050194590A1

    公开(公告)日：2005-09-08

    申请号：US11068778

    申请日：2005-03-02

    申请人： Hiroshi Matsushita ,  Tomonobu Noda ,  Kenichi Kadota ,  Junji Sugamoto ,  Yukihiro Ushiku

    发明人： Hiroshi Matsushita ,  Tomonobu Noda ,  Kenichi Kadota ,  Junji Sugamoto ,  Yukihiro Ushiku

    IPC分类号： H01L21/66 ,  G01R31/26 ,  H01L21/02 ,  H01L23/58

    CPC分类号： H01L22/20 ,  G01R31/2894 ,  G05B23/0248 ,  G05B2219/31357 ,  Y02P90/14

    摘要： A control system for a manufacturing apparatus includes manufacturing information input unit acquiring time series data of apparatus parameters controlling manufacturing apparatuses; failure pattern classification module classifying in-plane distributions of failures of each of the wafers into failure patterns; an index calculation unit configured to statistically process the time series data by algorithms to calculate indices corresponding to the respective algorithms; an index analysis unit providing first and second frequency distributions of the indices categorized with and without the target failure pattern, to implement significance test between the first and second frequency distributions; and an abnormal parameter extraction unit extracting failure cause index of failure pattern by comparing value of the significance test with test reference value.

    摘要翻译： 一种制造装置的控制系统，包括制造信息输入单元，其获取控制制造装置的装置参数的时间序列数据; 故障模式分类模块将每个晶片的故障平面内分布分为故障模式; 索引计算单元，被配置为通过算法对所述时间序列数据进行统计处理，以计算与各个算法对应的索引; 索引分析单元，提供分类有和没有目标故障模式的索引的第一和第二频率分布，以实现第一和第二频率分布之间的显着性测试; 异常参数提取单元通过比较显着性检验值与检测参考值，提取失效原因指标的故障模式。

    Semiconductor device and method of manufacturing the same
    47.
    发明授权
    Semiconductor device and method of manufacturing the same 有权

    公开(公告)号：US06724045B1

    公开(公告)日：2004-04-20

    申请号：US09713251

    申请日：2000-11-16

    申请人： Yukihiro Ushiku

    发明人： Yukihiro Ushiku

    IPC分类号： H01L310392

    CPC分类号： H01L21/76281 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/785 ,  H01L29/78612 ,  H01L29/78696 ,  H01L29/7881

    摘要： In a semiconductor device having a semiconductor element having a plurality of SOI-Si layers, the height of element isolation regions from the surface of the semiconductor substrate are substantially equal to each other. Alternatively, the element isolation regions are formed at the equal height on the semiconductor substrate and then a plurality of SOI-Si layers appropriately different in thickness are formed. In this manner, it is possible to obtain element isolation regions having substantially the same height from the semiconductor substrate and desired element regions having SOI-Si layers different in height. The thickness of a single crystalline silicon film (SOI-Si layer) may be appropriately changed by another method which includes depositing an amorphous silicon film and applying a heat processing to form an epi layer, and removing an unnecessary portion.

    Method of manufacturing insulated-gate type field effect transistor
    49.
    发明授权
    Method of manufacturing insulated-gate type field effect transistor 失效
    绝缘栅型场效应晶体管的制造方法

    公开(公告)号：US5185279A

    公开(公告)日：1993-02-09

    申请号：US673669

    申请日：1991-03-22

    申请人： Yukihiro Ushiku

    发明人： Yukihiro Ushiku

    IPC分类号： H01L21/266 ,  H01L21/336 ,  H01L21/8238

    CPC分类号： H01L29/66575 ,  H01L21/266 ,  H01L21/823807 ,  H01L29/6656 ,  Y10S148/082

    摘要： A method of manufacturing an insulated-gate type field effect transistor includes the steps of forming an insulating film, on a semiconductor substrate, forming a first polycrystalline silicon layer on the insulating film, forming a second polycrystalline silicon layer on the frist polycrystalline silicon layer, patterning the first and second polycrystalline silicon layers to form a gate electrode and a masking layer, doping an impurity of a first conductivity type in the semiconductor substrate using the gate electrode and the masking layer as masks, thereby forming a source region and a drain region, starting etching the masking layer, detecting a natural oxide film on the gate electrode, stopping the etching, and ion-implanting an impurity of a second conductivity type in a region of the semiconductor substrate under the gate electrode through the gate electrode, thereby forming a channel-doped region. In this method, after the source and drain regions are formed, the impurity of the second conductivity type is ion-implanted in the substrate through the thin gate electrode to form the channel-doped region.

    摘要翻译： 一种制造绝缘栅型场效应晶体管的方法包括以下步骤：在半导体衬底上形成绝缘膜，在绝缘膜上形成第一多晶硅层，在第一多晶硅层上形成第二多晶硅层; 构图第一和第二多晶硅层以形成栅电极和掩模层，使用栅电极和掩模层作为掩模在半导体衬底中掺杂第一导电类型的杂质，由此形成源区和漏区 ，开始蚀刻掩模层，检测栅电极上的自然氧化膜，停止蚀刻，并通过栅电极在栅电极下的半导体衬底的区域中离子注入第二导电类型的杂质，从而形成 沟道掺杂区域。 在该方法中，在形成源极和漏极区之后，通过薄栅电极将第二导电类型的杂质离子注入衬底中以形成沟道掺杂区。

    Clock driver distribution system in a semiconductor integrated circuit device
    50.
    发明授权
    Clock driver distribution system in a semiconductor integrated circuit device 失效
    半导体集成电路器件中的时钟驱动器分配系统

    公开(公告)号：US4661721A

    公开(公告)日：1987-04-28

    申请号：US767847

    申请日：1985-08-21

    申请人： Yukihiro Ushiku

    发明人： Yukihiro Ushiku

    IPC分类号： H03K5/00 ,  G06F1/10 ,  H03K5/15 ,  H03K19/01

    CPC分类号： G06F1/10

    摘要： A semiconductor integrated circuit device wherein a plurality of clock signal lines provided with a clock signal are drawn out independently from the respective output terminals of a plurality of divided clock drivers, the clock signal lines being connected together by a common connecting line.

    摘要翻译： 一种半导体集成电路器件，其中设置有时钟信号的多个时钟信号线与多个分频时钟驱动器的各个输出端独立地被抽出，时钟信号线通过公共连接线连接在一起。