公开(公告)号：US20080251683A1

公开(公告)日：2008-10-16

申请号：US12089783

申请日：2006-09-21

申请人： Thomas Paatzsch ,  Ingo Smaglinski ,  Martin Popp ,  Thomas Petigk

发明人： Thomas Paatzsch ,  Ingo Smaglinski ,  Martin Popp ,  Thomas Petigk

IPC分类号： F16M13/00 ,  G02B7/00

CPC分类号： G02B7/008 ,  G02B6/4226 ,  Y10T403/217

摘要： The invention concerns a structure comprising a first and a second component and a connecting element which connects the two components and which has at least two spring elements. In order to provide a structure and in particular an optical structure of the above-mentioned kind in which the two components have an extremely high level of positional and angular accuracy relative to each other even with major fluctuations in temperature it is proposed according to the invention that each spring element has a spring constant at least twice as great in two respective mutually perpendicular spatial directions as in the third spatial direction perpendicular to the first two spatial directions, referred to as the elasticity direction, wherein the two spring elements have elasticity directions which do not extend parallel to each other.

摘要翻译： 本发明涉及包括第一和第二部件以及连接两个部件并具有至少两个弹簧元件的连接元件的结构。 为了提供一种结构，特别是上述类型的光学结构，其中两个部件相对于彼此具有非常高的位置和角度准确度，即使在主要的温度波动下，根据本发明提出了 每个弹簧元件的弹簧常数在垂直于前两个空间方向的第三空间方向（称为弹性方向）的两个相应的相互垂直的空间方向上至少是两倍，其中两个弹簧元件具有弹性方向， 不要彼此平行延伸。

公开(公告)号：US20080217672A1

公开(公告)日：2008-09-11

申请号：US11684033

申请日：2007-03-09

申请人： Martin Popp ,  Ulrike Gruening-von Schwerin ,  Till Schloesser ,  Peter Lahnor ,  Rolf Weis ,  Odo Wunnicke

发明人： Martin Popp ,  Ulrike Gruening-von Schwerin ,  Till Schloesser ,  Peter Lahnor ,  Rolf Weis ,  Odo Wunnicke

IPC分类号： H01G4/40 ,  H01L21/62 ,  H01L27/01

CPC分类号： H01L27/10817 ,  H01G4/38 ,  H01G4/40 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/91

摘要： An integrated circuit having a memory arrangement including capacitor elements and further capacitor elements is disclosed. One embodiment provides a substrate layer with contact pads and further contact pads; the capacitor elements being disposed in a first level on the substrate layer and connected with the contact pads; the further capacitor elements being disposed in a second level above the first level; contact elements being disposed between the capacitor elements and connected with the further contact pads; the further capacitor elements being disposed above the contact elements and being connected with the contact elements.

摘要翻译： 公开了具有包括电容器元件和其它电容器元件的存储器布置的集成电路。 一个实施例提供具有接触垫和另外的接触垫的衬底层; 所述电容器元件设置在所述基底层上的第一层中并与所述接触垫相连接; 所述另外的电容器元件设置在高于所述第一电平的第二电平; 接触元件设置在电容器元件之间并与另外的接触垫连接; 另外的电容器元件设置在接触元件上方并与接触元件连接。

公开(公告)号：US20070290249A1

公开(公告)日：2007-12-20

申请号：US11844853

申请日：2007-08-24

申请人： Martin Popp ,  Frank Jakubowski ,  Juergen Holz ,  Lars Heineck

发明人： Martin Popp ,  Frank Jakubowski ,  Juergen Holz ,  Lars Heineck

IPC分类号： H01L29/94

CPC分类号： H01L29/945 ,  H01L21/26586 ,  H01L27/0207 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894

摘要： An integrated circuit includes a memory cell array comprising memory cells with a transistor. The transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed under the bottom side of each word line. In addition, the word lines are disposed over the bit lines.

摘要翻译： 集成电路包括具有晶体管的存储单元的存储单元阵列。 晶体管形成在有源区域中。 存储单元阵列还包括沿第一方向定向的位线和朝向第二方向的字线。 有源区域沿第二方向延伸。 晶体管的每个栅电极的底侧设置在每个字线的底侧的下方。 此外，字线设置在位线之上。

公开(公告)号：US20070075361A1

公开(公告)日：2007-04-05

申请号：US11529446

申请日：2006-09-28

申请人： Richard Luyken ,  Hans-Peter Moll ,  Martin Popp ,  Till Schloesser ,  Marc Strasser ,  Rolf Weis

发明人： Richard Luyken ,  Hans-Peter Moll ,  Martin Popp ,  Till Schloesser ,  Marc Strasser ,  Rolf Weis

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L21/26586 ,  H01L29/66537 ,  H01L29/66621 ,  H01L29/7834

摘要： In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.

摘要翻译： 在制造沟槽晶体管的方法中，提供第一导电类型的衬底，并且形成衬底中的沟槽和沟槽中的栅极电介质。 形成沟槽中作为栅极电介质和第一源极和漏极区域上的栅电极的第一导电填充物。 蚀刻后的第一导电填充物是通过将第一导电填料向下蚀刻回到低于第一源的深度并形成漏极区和第二源极和漏极区而产生的。 第二源极和漏极区域与第一源极和漏极区域相邻并且延伸至至少与蚀刻后的第一导电填充物一样深的深度。 在所述沟槽中形成有在所述蚀刻后的第一导电填充物上方的绝缘间隔物，并且在所述沟槽中设置第二导电填充物作为所述栅电极的上部。

公开(公告)号：US20060231918A1

公开(公告)日：2006-10-19

申请号：US10482328

申请日：2002-06-19

申请人： Martin Popp ,  Frank Richter ,  Dietmar Temmler ,  Andreas Wich-Glasen

发明人： Martin Popp ,  Frank Richter ,  Dietmar Temmler ,  Andreas Wich-Glasen

IPC分类号： H01L29/00

CPC分类号： H01L29/7851 ,  H01L21/76229 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66651

摘要： A transistor is provided which advantageously utilizes a part of the area which, in conventional transistors, is provided for the isolation between the transistors. In this case, the channel width can be enlarged in a self-aligned manner without the risk of short circuits. The field-effect transistor according to the invention has the advantage that it is possible to ensure a significant increase in the effective channel width for the forward current ION compared with previously used, conventional transistor structures, without having to accept a reduction of the integration density that can be attained. Thus, by way of example, the forward current ION can be increased by up to 50%, without having to alter the arrangement of the active regions or of the trench isolation.

摘要翻译： 提供了一种晶体管，其有利地利用了在常规晶体管中提供用于晶体管之间的隔离的区域的一部分。 在这种情况下，可以以自对准的方式扩大通道宽度，而不会出现短路的风险。 根据本发明的场效应晶体管的优点在于，与先前使用的传统晶体管结构相比，可以确保正向电流ION的有效沟道宽度的显着增加，而不必接受集成密度的降低 可以实现。 因此，作为示例，正向电流I ON ON可以增加高达50％，而不必改变有源区域或沟槽隔离的布置。

公开(公告)号：US06977405B2

公开(公告)日：2005-12-20

申请号：US10792742

申请日：2004-03-05

申请人： Jörn Lützen ,  Bernd Goebel ,  Dirk Schumann ,  Martin Gutsche ,  Harald Seidl ,  Martin Popp ,  Alfred Kersch ,  Werner Steinhögl

发明人： Jörn Lützen ,  Bernd Goebel ,  Dirk Schumann ,  Martin Gutsche ,  Harald Seidl ,  Martin Popp ,  Alfred Kersch ,  Werner Steinhögl

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L27/10891

摘要： In order to fabricate a semiconductor memory, a trench capacitor is arranged in a first trench. Beside the first trench, a first longitudinal trench and, parallel on the other side of the first trench, a second longitudinal trench are arranged in the substrate. A first spacer word line is arranged in the first longitudinal trench and a second spacer word line is arranged in the second longitudinal trench. There are arranged in the first trench connecting webs between the first spacer word line and the second spacer word line which have a thickness which, in the direction of the first spacer word line, is less than half the width of the first trench in the direction of the first spacer word line.

摘要翻译： 为了制造半导体存储器，在第一沟槽中布置有沟槽电容器。 在第一沟槽的旁边，在衬底中布置有第一纵向沟槽，并且在第一沟槽的另一侧平行的第二纵向沟槽。 第一间隔字线布置在第一纵向沟槽中，第二间隔字线布置在第二纵向沟槽中。 布置在第一沟槽中，连接腹板之间的第一隔离物字线和第二隔离物字线之间的厚度，该厚度在第一隔离物字线的方向上小于第一沟槽的方向上的宽度的一半 的第一个间隔字线。

公开(公告)号：US20050031256A1

公开(公告)日：2005-02-10

申请号：US10490007

申请日：2002-08-07

申请人： Thomas Paatzsch ,  Martin Popp ,  Ingo Smaglinski

发明人： Thomas Paatzsch ,  Martin Popp ,  Ingo Smaglinski

IPC分类号： G02B6/34 ,  G02B6/26

CPC分类号： G02B6/29365 ,  G02B6/29395 ,  G02B6/29398

摘要： A temperature compensation method for an optical component using at least one cut-off or band-pass filter and beam-guiding optics is provided. An object of the invention is to provide a method with which an optical component can be operated with a temperature-dependent band pass, or cut-off filter across a wide range of temperatures. The method features orientation of the beam relative to the cut-off or band pass filter which changes subject to the temperature of the component.

摘要翻译： 提供了使用至少一个截止或带通滤波器和光束引导光学器件的光学部件的温度补偿方法。 本发明的目的是提供一种可以在宽范围的温度范围内使用温度依赖带通或截止滤波器来操作光学部件的方法。 该方法具有相对于截止或带通滤波器的光束取向，其随组件的温度而变化。

公开(公告)号：US08977080B2

公开(公告)日：2015-03-10

申请号：US13123258

申请日：2009-10-02

申请人： Ingo Smaglinski ,  Thomas Petigk ,  Martin Popp ,  Samuel Brantzen ,  Thomas Paatzsch

发明人： Ingo Smaglinski ,  Thomas Petigk ,  Martin Popp ,  Samuel Brantzen ,  Thomas Paatzsch

IPC分类号： G02B6/26 ,  G02B6/42 ,  H04J14/02 ,  G02B6/293

CPC分类号： G02B6/4215 ,  G02B6/29365 ,  G02B6/4214 ,  G02B6/4225

摘要： The present invention relates to a multiplexer/demultiplexer with a connection for inputting and/or outputting an optical signal which has signal components of different wavelengths, a carrier plate (8) with at least one wavelength-sensitive element (11), a focussing member (13) with at least two focussing elements (14, 14′) as well as a detector or signal-generator plate (1), on which at least two detectors (4) or signal generators are arranged. To achieve this object, it is proposed according to the invention that both carrier plate (8) and focussing member (13) are connected to the detector or signal-generator plate (1).

摘要翻译： 本发明涉及具有用于输入和/或输出具有不同波长的信号分量的光信号的连接的多路复用器/解复用器，具有至少一个波长敏感元件（11）的载板（8），聚焦部件 （13）具有至少两个聚焦元件（14,14'）以及检测器或信号发生器板（1），其上布置有至少两个检测器（4）或信号发生器。 为了实现这个目的，根据本发明提出了承载板（8）和聚焦构件（13）都连接到检测器或信号发生器板（1）。

公开(公告)号：US08901690B2

公开(公告)日：2014-12-02

申请号：US13551732

申请日：2012-07-18

申请人： Martin Popp ,  Beat De Coi ,  Marco Annese

发明人： Martin Popp ,  Beat De Coi ,  Marco Annese

IPC分类号： H01L27/146 ,  H01L27/148 ,  H01L31/18 ,  H01L31/0216 ,  H01L31/0232 ,  H01L31/101

CPC分类号： H01L27/1463

摘要： A semiconductor structure for photon detection, comprising a substrate composed of a semiconductor material having a first doping, a contact region fitted at the frontside of the substrate, a bias layer composed of a semiconductor material having a second doping, which is arranged on the backside of the substrate at a distance from the contact region, wherein the contact region at least partly lies opposite the bias layer, such that an overlap region is present in a lateral direction, a guard ring, which is arranged at the frontside of the substrate and surrounds the contact region, wherein a reverse voltage can be applied between the contact region and the guard ring. In order to enable more cost-effective production, the overlap region has a lateral extent amounting to at least one quarter of the distance between contact region and bias layer.

摘要翻译： 一种用于光子检测的半导体结构，包括由具有第一掺杂的半导体材料构成的衬底，安装在衬底的前侧的接触区域，由具有第二掺杂的半导体材料组成的偏置层，其布置在背面 所述接触区域至少部分地与所述偏置层相对，使得重叠区域在横向方向上存在，保护环布置在所述基板的前侧，并且所述保护环设置在所述基板的前侧;以及 围绕接触区域，其中可以在接触区域和保护环之间施加反向电压。 为了实现更具成本效益的生产，重叠区域具有等于接触区域和偏置层之间的距离的至少四分之一的横向范围。

公开(公告)号：US08802566B2

公开(公告)日：2014-08-12

申请号：US13593933

申请日：2012-08-24

申请人： Martin Popp ,  Beat De Coi ,  Marco Annese

发明人： Martin Popp ,  Beat De Coi ,  Marco Annese

IPC分类号： G03F7/20 ,  H01L29/96 ,  H01L21/3213 ,  H01L21/033

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338

摘要： A method for producing semiconductor components on a substrate including photolithographic patterning steps, in which method, on the substrate, a first layer to be patterned is applied and a second layer serving as a mask layer for the first layer to be patterned is applied, wherein a third layer serving as a mask for the second layer is applied, and wherein at least two photolithographic patterning processes are carried out successively for the second layer, wherein, during one of the patterning processes, after the production of a structure made from a photosensitive layer for the provision of a mask layer for a patterning process at the third layer, positive ramp angles α are produced at the patterning edges of the third layer, as a result of which the structures remaining free, given a thickness h of the third layer, decrease in size by a value D=2*h/tan α.

摘要翻译： 一种用于在包括光刻图案步骤的基板上制造半导体部件的方法，其中施加了在基板上形成要构图的第一层的方法，并且施加用作待图案化第一层的掩模层的第二层，其中 施加用作第二层的掩模的第三层，并且其中对于第二层连续执行至少两个光刻图案化工艺，其中在一个图案化工艺期间，在制造由感光材料制成的结构之后 层，用于在第三层提供用于图案化工艺的掩模层，在第三层的图案化边缘处产生正斜面角α，结果，给定第三层的厚度h，结构保持游离 ，尺寸减小值D = 2 * h /tanα。