公开(公告)号：US20120161820A1

公开(公告)日：2012-06-28

申请号：US13288893

申请日：2011-11-03

申请人： Bon-Yong Koo ,  Sung-Man Kim ,  Jae-Hoon Lee

发明人： Bon-Yong Koo ,  Sung-Man Kim ,  Jae-Hoon Lee

IPC分类号： H03K3/00 ,  H01L33/08

CPC分类号： H01L27/1259 ,  G09G3/3611 ,  H01L27/1255 ,  H01L29/41733

摘要： A gate drive circuit includes plural stages connected together one after each other. Each of the plural stages includes a circuit transistor, a capacitor part, a first connection part and a second connection part. The circuit transistor outputs the gate signal through a source electrode in response to a control signal applied through a gate electrode. The capacitor part includes a first electrode, a second electrode formed on the first electrode, and a third electrode formed on the second electrode. The first connection part electrically connects the gate electrode of the circuit transistor and the second electrode of the capacitor part. The second connection part electrically connects the source electrode of the circuit transistor and the first electrode of the capacitor part. Thus, an integrated size of a gate drive circuit may be decreased, and a reliability of a gate drive circuit may be enhanced.

摘要翻译： 栅极驱动电路包括一个接一个地连接在一起的多个级。 多级中的每一个包括电路晶体管，电容器部分，第一连接部分和第二连接部分。 响应于通过栅电极施加的控制信号，电路晶体管通过源电极输出栅极信号。 电容器部分包括第一电极，形成在第一电极上的第二电极和形成在第二电极上的第三电极。 第一连接部电连接电路晶体管的栅电极和电容器部的第二电极。 第二连接部分电连接电路晶体管的源电极和电容器部分的第一电极。 因此，可以减小栅极驱动电路的集成尺寸，并且可以提高栅极驱动电路的可靠性。

公开(公告)号：US20090014727A1

公开(公告)日：2009-01-15

申请号：US12172701

申请日：2008-07-14

申请人： Sung-Man Kim ,  Young-Goo Song ,  Hyang-Shik Kong ,  Dong-Hyun Ki ,  Seong-Young Lee ,  Joo-Ae Yoon ,  Jong-Woong Chang

发明人： Sung-Man Kim ,  Young-Goo Song ,  Hyang-Shik Kong ,  Dong-Hyun Ki ,  Seong-Young Lee ,  Joo-Ae Yoon ,  Jong-Woong Chang

IPC分类号： H01L29/04 ,  H01L21/336

CPC分类号： H01L27/016 ,  G02F1/13458 ,  G02F1/136227 ,  H01L27/12 ,  H01L27/1244 ,  H01L27/1248 ,  H01L27/1288 ,  H01L27/3244 ,  H01L29/456 ,  H01L29/4908

摘要： A thin film array panel is provided, which includes: a plurality of signal lines including contact parts for contact with an external device; a plurality of thin film transistors connected to the signal lines; an insulating layer formed on the signal lines and the thin film transistors; and a plurality of pixel electrodes formed on the insulating layer and connected to the thin film transistors, wherein the insulating layer includes a contact portion disposed on the contact parts of the signal lines and having a thickness smaller than other portions and the contact portion of the insulating layer includes an inclined portion having an inclination angle smaller than about 45 degrees.

摘要翻译： 提供一种薄膜阵列面板，其包括：多条信号线，包括用于与外部装置接触的接触部分; 连接到信号线的多个薄膜晶体管; 形成在信号线和薄膜晶体管上的绝缘层; 以及形成在所述绝缘层上并连接到所述薄膜晶体管的多个像素电极，其中所述绝缘层包括设置在所述信号线的接触部分上并具有小于其它部分的厚度的接触部分，并且所述接触部分 绝缘层包括具有小于约45度的倾斜角度的倾斜部分。

公开(公告)号：US20060270205A1

公开(公告)日：2006-11-30

申请号：US11498197

申请日：2006-08-03

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

IPC分类号： H01L21/4763 ,  H01L23/52

CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

公开(公告)号：US07098123B2

公开(公告)日：2006-08-29

申请号：US10780244

申请日：2004-02-17

申请人： Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim ,  Si-Young Choi ,  Gil-Heyun Choi ,  Ja-Hum Ku ,  Chang-Won Lee ,  Jong-Myeong Lee ,  Kwon-Sun Ryu

发明人： Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim ,  Si-Young Choi ,  Gil-Heyun Choi ,  Ja-Hum Ku ,  Chang-Won Lee ,  Jong-Myeong Lee ,  Kwon-Sun Ryu

IPC分类号： H01L21/28

CPC分类号： H01L21/28061 ,  H01L21/28088 ,  H01L29/4941 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon pattern and a metal-gate pattern. An oxidation barrier layer is formed to cover at least a portion of a sidewall of the metal-gate pattern.

摘要翻译： 形成具有金属栅电极的半导体器件的方法包括在半导体衬底上顺序地形成栅极绝缘体，栅极多晶硅层和金属栅极层。 金属栅极层和栅极多晶硅层被顺序地图案化以形成包括堆叠栅极多晶硅图案和金属栅极图案的栅极图案。 形成氧化阻挡层以覆盖金属 - 栅极图案的侧壁的至少一部分。

公开(公告)号：US20060056267A1

公开(公告)日：2006-03-16

申请号：US11224671

申请日：2005-09-12

申请人： Sung-Man Kim ,  Seong-Young Lee ,  Yeon-Kyu Moon ,  Yun-Hee Kwak ,  Jong-Woong Chang

发明人： Sung-Man Kim ,  Seong-Young Lee ,  Yeon-Kyu Moon ,  Yun-Hee Kwak ,  Jong-Woong Chang

IPC分类号： G11C8/00 ,  G11C5/06

CPC分类号： G09G3/3677 ,  G09G2300/0426 ,  G09G2330/08

摘要： In a driving unit (e.g., a gate driving unit) and a flat panel display apparatus having the driving unit, a circuit portion of the driving unit includes a plurality of driving stages cascade-connected to one another and outputs a (gate) driver signal (a plurality of gate-driving signals) based on a plurality of control signals. The line portion comprises a first signal line and a second signal line, each of which transmits control signals from the outside, and a first connection line connecting the first signal line to the driving stages, and a second connection line connecting the second signal line to the driving stages. The second signal line is positioned at a different (metallization) layer from the first signal line and the first and second connection lines. Therefore, malfunctioning of the driving unit caused by corrosion may be prevented.

摘要翻译： 在驱动单元（例如，门驱动单元）和具有驱动单元的平板显示装置中，驱动单元的电路部分包括彼此串联连接的多个驱动级并输出（门）驱动信号 （多个栅极驱动信号）。 线路部分包括第一信号线和第二信号线，每条信号线和第二信号线都从外部发送控制信号，第一连接线将第一信号线连接到驱动级，第二连接线将第二信号线连接到 驾驶阶段。 第二信号线位于与第一信号线和第一和第二连接线不同的（金属化）层。 因此，可以防止由腐蚀引起的驱动单元的故障。

公开(公告)号：US20060054889A1

公开(公告)日：2006-03-16

申请号：US10942039

申请日：2004-09-16

申请人： Jang-Soo Kim ,  Hyang-Shik Kong ,  Hye-Young Ryu ,  Sung-Man Kim

发明人： Jang-Soo Kim ,  Hyang-Shik Kong ,  Hye-Young Ryu ,  Sung-Man Kim

IPC分类号： H01L29/04

CPC分类号： H01L27/124 ,  G02F1/136213 ,  G02F1/136259 ,  G02F2001/13629 ,  H01L27/1255 ,  H01L27/1288

摘要： A thin film transistor array panel comprising: an insulating substrate; a plurality of gate lines formed on the insulating substrate and including a plurality of gate electrodes and end portions; a plurality of storage electrode lines formed on the insulating substrate; a gate insulating layer formed on the gate lines and storage electrode lines; a semiconductor layer formed on the gate insulating layer; a ohmic contact layer formed on the semiconductor layer; a plurality of data lines formed on the gate insulating layer, intersecting the gate lines to define a display area, and having source electrodes and end portions; a plurality of drain electrodes facing the source electrodes; a passivation layer formed on the data lines and drain electrodes and having contact holes; a plurality of pixel electrodes formed on the passivation layer and connected to the drain electrodes through the contact holes; a storage line connecting bar connecting the storage electrode lines; and a redundant connecting line connecting the storage electrode lines is provided.

摘要翻译： 1.一种薄膜晶体管阵列面板，包括：绝缘基板; 多个栅极线，形成在所述绝缘基板上并且包括多个栅电极和端部; 形成在所述绝缘基板上的多个存储电极线; 形成在栅极线和存储电极线上的栅极绝缘层; 形成在所述栅极绝缘层上的半导体层; 形成在所述半导体层上的欧姆接触层; 形成在所述栅极绝缘层上的多条数据线，与所述栅极线交叉以限定显示区域，并具有源电极和端部; 面对所述源电极的多个漏电极; 形成在数据线和漏电极上并具有接触孔的钝化层; 多个像素电极，形成在钝化层上并通过接触孔连接到漏电极; 连接存储电极线的存储线连接条; 并且提供连接存储电极线的冗余连接线。

公开(公告)号：US09659542B2

公开(公告)日：2017-05-23

申请号：US11230112

申请日：2005-09-19

申请人： Haeng-Won Park ,  Seung-Hwan Moon ,  Nam-Soo Kang ,  Sung-Jae Moon ,  Sung-Man Kim ,  Seong-Young Lee ,  Yong-Soon Lee

发明人： Haeng-Won Park ,  Seung-Hwan Moon ,  Nam-Soo Kang ,  Sung-Jae Moon ,  Sung-Man Kim ,  Seong-Young Lee ,  Yong-Soon Lee

IPC分类号： G09G5/00 ,  G09G3/36 ,  G11C19/18

CPC分类号： G09G3/3677 ,  G09G2300/0426 ,  G11C19/184

摘要： A gate driver includes multiple stages. Each stage has a circuit portion and a wiring portion. The wiring portion delivers first and second clock signals to the circuit portion. Further, the wiring portion includes first and second clock wirings receiving the first and second clock signal, respectively, first connecting wirings electrically connecting the first clock wiring with a first every other stage, and second connecting wirings electrically connecting the second clock wiring with the odd-numbered stages. Further, the wiring portion includes third connecting wirings electrically connecting the first connecting wiring with a second every other stage and fourth connecting wirings electrically connecting the second connecting wiring with the even-numbered stages. This configuration may prevent the gate driver from operating erroneously and reduce power consumed by the gate driver.

公开(公告)号：US08681083B2

公开(公告)日：2014-03-25

申请号：US11109607

申请日：2005-04-18

申请人： Nam-Soo Kang ,  Seong-Young Lee ,  Sung-Man Kim ,  Seung-Hwan Moon

发明人： Nam-Soo Kang ,  Seong-Young Lee ,  Sung-Man Kim ,  Seung-Hwan Moon

IPC分类号： G09G3/36

CPC分类号： G09G3/3614 ,  G02F1/136286 ,  G09G3/36 ,  G09G3/3611 ,  G09G3/3648 ,  G09G3/3655 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2310/08 ,  G09G2320/0209 ,  G09G2320/0247

摘要： A display device includes a pixel matrix having pixel rows and pixel columns and including pixels having switching elements positioned alternately at a corner near an upper and a lower side of each pixel row and positioned alternately at a corner near an upper and a lower side of and alternately at a corner near a left and a right side of each pixel column; multiple pairs of gate lines transmitting a gate-on voltage; and multiple data lines transmitting data voltages, wherein each pair of gate lines are disposed at the upper and lower sides of each pixel row with the pixels in each row connected to the gate line positioned nearest the respective switching element, and each data line is disposed between adjacent pairs of pixel columns and connected to pairs of pixels where one pixel of the pair has a switching element positioned nearest the respective data line.

公开(公告)号：US08457563B2

公开(公告)日：2013-06-04

申请号：US12565296

申请日：2009-09-23

申请人： Sung-Man Kim ,  Myung-Kwang Byun ,  Byung-Joon Park ,  Seong-Yong Park

发明人： Sung-Man Kim ,  Myung-Kwang Byun ,  Byung-Joon Park ,  Seong-Yong Park

IPC分类号： H04B17/00

CPC分类号： H04L25/0242

摘要： A calibration apparatus and method for supporting a Relay Station (RS) in a multiple antenna communication system are provided. The calibration method in the multiple antenna communication system which supports the RS includes, when a modem stage sends a downlink calibration signal, receiving, at a calibrator, the downlink calibration signal and estimating a downlink path channel, when the calibrator sends an uplink calibration signal, receiving, at the modem stage, the uplink calibration signal and estimating an uplink path channel, determining, at the modem stage, calibration coefficients per path not to generate a phase and amplitude difference with respect to the estimated uplink path channel and the estimated downlink path channel, and applying the calibration coefficients per path to corresponding antennas respectively.

摘要翻译： 提供了一种用于在多天线通信系统中支持中继站（RS）的校准装置和方法。 支持RS的多天线通信系统中的校准方法包括当调制解调器级发送下行链路校准信号时，在校准器处接收下行链路校准信号并估计下行链路路径信道，当校准器发送上行链路校准信号 在调制解调器阶段接收上行链路校准信号并估计上行链路路径信道，在调制解调器阶段确定每个路径的校准系数不相对于估计的上行链路路径信道和估计的下行链路信道产生相位和幅度差 路径信道，并将每个路径的校准系数分别应用于相应的天线。

公开(公告)号：US08254997B2

公开(公告)日：2012-08-28

申请号：US12657321

申请日：2010-01-19

申请人： Sung-Man Kim ,  Jun-Sung Lee ,  Seong-Yong Park

发明人： Sung-Man Kim ,  Jun-Sung Lee ,  Seong-Yong Park

IPC分类号： H04B1/38

CPC分类号： H04B17/21

摘要： A base station is capable of performing 4-beamforming using Radio Units (RU), each having two paths in a wireless communication system. The base station includes a Digital Unit (DU), a first RU, and a second RU. The DU performs a mutual conversion function between an information bit line and a digital signal, calculates beamforming coefficients for 4-beamforming, and performs the 4-beamforming using the beamforming coefficients. The first RU has two Radio Frequency (RF) paths, extracts a clock signal from a digital signal from the DU, and provides the clock signal to the second RU. The second RU has two RF paths and operates according to the clock signal provided from the first RU.

摘要翻译： 基站能够使用无线电单元（RU）来执行四波束成形，每个单元在无线通信系统中具有两条路径。 基站包括数字单元（DU），第​​一RU和第二RU。 DU在信息位线和数字信号之间执行相互转换功能，计算4波束成形的波束形成系数，并使用波束成形系数执行4波束成形。 第一RU具有两个射频（RF）路径，从DU的数字信号中提取时钟信号，并将时钟信号提供给第二RU。 第二RU具有两个RF路径，并且根据从第一RU提供的时钟信号进行操作。