公开(公告)号：US20090108831A1

公开(公告)日：2009-04-30

申请号：US12328893

申请日：2008-12-05

申请人： Kalle LEVON ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

发明人： Kalle LEVON ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

IPC分类号： G01N27/00

CPC分类号： G01N27/4145 ,  G01N27/4148

摘要： Specific ionic interactions with a sensing material that is electrically coupled with the floating gate of a floating gate-based ion sensitive field effect transistor (FGISFET) may be used to sense a target material. For example, an FGISFET can use (e.g., previously demonstrated) ionic interaction-based sensing techniques with the floating gate of floating gate field effect transistors. The floating gate can serves as a probe and an interface to convert chemical and/or biological signals to electrical signals, which can be measured by monitoring the change in the device's threshold voltage, VT.

摘要翻译： 可以使用与浮置栅极离子敏感场效应晶体管（FGISFET）的浮动栅极电耦合的感测材料的特定离子相互作用来感测目标材料。 例如，FGISFET可以使用浮动栅极场效应晶体管的浮动栅极（例如，先前证明的）基于离子相互作用的感测技术。 浮动栅极可以用作探测器和将化学和/或生物信号转换为电信号的接口，这可以通过监测器件的阈值电压VT的变化来测量。

公开(公告)号：US07518398B1

公开(公告)日：2009-04-14

申请号：US11973062

申请日：2007-10-04

申请人： Arifur Rahman ,  Stephen M. Trimberger ,  Bernard J. New

发明人： Arifur Rahman ,  Stephen M. Trimberger ,  Bernard J. New

IPC分类号： H03K19/173

CPC分类号： H03K19/17796

摘要： An integrated circuit with a through-die via (TDV) interface for die stacking is described. One aspect of the invention relates to an integrated circuit die having an array of tiles arranged in columns. The integrated circuit die includes at least one interface tile. Each interface tile includes a logic element, contacts, and through die vias (TDVs). The logic element is coupled to a routing fabric of the integrated circuit die. The contacts are configured to be coupled to conductive interconnect of another integrated circuit die attached to the backside of the integrated circuit die. The TDVs are configured to couple the logic element to the contacts.

摘要翻译： 描述了具有用于管芯堆叠的通孔（TDV）接口的集成电路。 本发明的一个方面涉及具有排列成列的瓷砖阵列的集成电路管芯。 集成电路管芯包括至少一个界面砖。 每个接口瓦片包括逻辑元件，触点和通孔（TDV）。 逻辑元件耦合到集成电路管芯的布线结构。 触点被配置为耦合到附接到集成电路管芯的背面的另一个集成电路管芯的导电互连。 TDV被配置为将逻辑元件耦合到触点。

公开(公告)号：US07298175B1

公开(公告)日：2007-11-20

申请号：US11158579

申请日：2005-06-22

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： H03K19/094

CPC分类号： H03K17/005 ,  H03K17/6257 ,  H03K17/693 ,  H03K2217/0036

摘要： An integrated circuit programmable multiplexer that reduces sub-threshold leakage current in deep sub-micron technology. The multiplexer uses a plurality of transistor stages, wherein each transistor of a subsequent stage is connected to at least two transistors of a prior stage, such that each transistor is in series with at least one other transistor. Transistors that are not part of the signal path through the multiplexer are deactivated, wherein a series of two or more deactivated transistors have significantly less sub-threshold leakage current than a single deactivated transistor. Configuration memory cells that store and communicate control signals to the multiplexer transistors are also connected to a low-voltage power supply when the multiplexer is not in use to reduce leakage current through the memory cells.

摘要翻译： 集成电路可编程多路复用器，可减少深亚微米技术中的亚阈值漏电流。 多路复用器使用多个晶体管级，其中后级的每个晶体管连接到前级的至少两个晶体管，使得每个晶体管与至少一个其它晶体管串联。 不是通过多路复用器的信号路径的一部分的晶体管被​​去激活，其中一系列两个或更多个去激活晶体管具有比单个去激活晶体管明显更少的次阈值漏电流。 当多路复用器不用于减少通过存储器单元的泄漏电流时，存储和传送控制信号到多路复用器晶体管的配置存储单元也连接到低压电源。

公开(公告)号：US07218168B1

公开(公告)日：2007-05-15

申请号：US11210497

申请日：2005-08-24

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： G05F1/10

CPC分类号： G05F1/56

摘要： A voltage regulator and a method for voltage regulation are described. An adjustable driver is coupled to receive an input voltage, a gating voltage, and first control signaling. The adjustable driver includes driver transistors. The adjustable driver is configured to provide a drive current responsive to the gating voltage. The drive current is provided through one or more of the driver transistors at least a portion of which are selectively gated responsive to the first control signaling. A controller is coupled to receive the input voltage and the gating voltage. The controller is configured to provide the first control signaling responsive to the gating voltage. Control circuitry is configured to provide the gating voltage responsive to load current.

摘要翻译： 描述了电压调节器和电压调节方法。 耦合可调节驱动器以接收输入电压，门控电压和第一控制信号。 可调驱动器包括驱动晶体管。 可调节驱动器被配置为提供响应于门控电压的驱动电流。 通过一个或多个驱动器晶体管提供驱动电流，其中至少一部分响应于第一控制信号而选择性选通。 控制器被耦合以接收输入电压和门控电压。 控制器被配置为响应于门控电压提供第一控制信号。 控制电路被配置为响应于负载电流提供门控电压。

公开(公告)号：US06788101B1

公开(公告)日：2004-09-07

申请号：US10366956

申请日：2003-02-13

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： H03K19003

CPC分类号： H04L25/0276 ,  H03K19/017581 ,  H04L25/028 ,  H04L25/0292

摘要： A programmable interface circuit is disclosed, in accordance with one embodiment, which supports differential and single-ended signaling. For example, an input buffer within the programmable interface circuit is configurable to receive differential signals or single-ended signals. A multiplexer provides the appropriate reference signal to the input buffer, when configured to receive single-ended signals, by selecting the reference signal from a plurality of reference buses. The multiplexer, along with a capacitor, may also provide lowpass filtering of the reference signal. Furthermore, an output buffer may be configurable utilizing techniques similar to that described for the input buffer.

公开(公告)号：US10132773B2

公开(公告)日：2018-11-20

申请号：US12328888

申请日：2008-12-05

申请人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

发明人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

IPC分类号： G01N27/414

摘要： Specific ionic interactions with a sensing material that is electrically coupled with the floating gate of a floating gate-based ion sensitive field effect transistor (FGISFET) may be used to sense a target material. For example, an FGISFET can use (e.g., previously demonstrated) ionic interaction-based sensing techniques with the floating gate of floating gate field effect transistors. The floating gate can serves as a probe and an interface to convert chemical and/or biological signals to electrical signals, which can be measured by monitoring the change in the device's threshold voltage, VT.

公开(公告)号：US09698123B2

公开(公告)日：2017-07-04

申请号：US13235166

申请日：2011-09-16

申请人： Arifur Rahman ,  Jon M. Long ,  Yuanlin Xie

发明人： Arifur Rahman ,  Jon M. Long ,  Yuanlin Xie

IPC分类号： H01L25/065 ,  H01L23/00 ,  H05K3/46 ,  H05K1/14

CPC分类号： H01L25/0652 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H05K1/141 ,  H05K3/4697 ,  H05K2201/1053 ,  H01L2924/014 ,  H01L2924/00

摘要： An apparatus includes a substrate and a pair of die that include electronic circuitry. The substrate includes a cavity. One of the die is disposed in the cavity formed in the substrate. The other die is disposed above the first die and is electrically coupled to the first die.

公开(公告)号：US08933345B1

公开(公告)日：2015-01-13

申请号：US12779739

申请日：2010-05-13

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： H05K1/11

CPC分类号： H01L23/147 ,  H01L22/14 ,  H01L22/34 ,  H01L23/5384 ,  H01L2224/16225 ,  H01L2924/15311

摘要： A silicon interposer has a plurality of conductive vias extending from a first side of a silicon substrate to an opposite side of the silicon substrate. A plurality of first side scan chain links are disposed on the first side of the silicon substrate. Each scan chain link electrically connects two conducting vias of the plurality of the conductive vias together. In some cases, a test fixture connects the opposite side of the conductive vias together and continuity or resistance is measured. In other cases, scan chain links are formed on the opposite side of the wafer to form a scan chain, which is electronically tested.

摘要翻译： 硅插入器具有从硅衬底的第一侧延伸到硅衬底的相对侧的多个导电通路。 多个第一侧扫描链节设置在硅衬底的第一侧上。 每个扫描链路链路将多个导电通孔中的两个导电通孔电连接在一起。 在某些情况下，测试夹具将导电通孔的相对侧连接在一起，并测量连续性或电阻。 在其他情况下，扫描链节形成在晶片的相对侧上以形成扫描链，其被电子测试。

公开(公告)号：US08886481B1

公开(公告)日：2014-11-11

申请号：US12835184

申请日：2010-07-13

申请人： Arifur Rahman ,  Michael J. Hart ,  Venkatesan Murali

发明人： Arifur Rahman ,  Michael J. Hart ,  Venkatesan Murali

IPC分类号： G06F19/00

CPC分类号： H01L22/20 ,  H01L22/14 ,  H01L2224/16225 ,  H01L2924/15311

摘要： A method of reducing variation in multi-die integrated circuits can include, for each of a plurality of dies, determining at least one performance metric and selecting at least two dies for inclusion within a multi-die integrated circuit according to the at least one performance metric. Systems and devices for executing the steps of the method are also described.

摘要翻译： 减少多管芯集成电路中的变化的方法可以包括对于多个管芯中的每一个，确定至少一个性能度量并且根据至少一个性能选择至少两个管芯以包括在多管芯集成电路内 度量。 还描述了用于执行该方法的步骤的系统和设备。

公开(公告)号：US08802454B1

公开(公告)日：2014-08-12

申请号：US13331702

申请日：2011-12-20

申请人： Arifur Rahman ,  Henley Liu ,  Cheang-Whang Chang ,  Myongseob Kim ,  Dong W. Kim

发明人： Arifur Rahman ,  Henley Liu ,  Cheang-Whang Chang ,  Myongseob Kim ,  Dong W. Kim

IPC分类号： H01L21/66

CPC分类号： H01L22/34 ,  H01L22/14

摘要： A method for testing TSVs is provided. A plurality of TSVs is formed in a semiconductor substrate. Wiring layers and a first contact array are formed on the front-side of the substrate. The wiring layers couple each of the TSVs to a respective contact of the first contact array. Conductive adhesive is deposited over the first contact array. The conductive adhesive electrically couples contacts of the first contact array. A carrier is bonded to the front-side of the substrate with the conductive adhesive. After bonding the carrier to the substrate, the back-side of the substrate is thinned to expose each of the TSVs on the back-side of the substrate. A second contact array is formed, having a contact coupled to each respective TSV. Conductivity and connections of the TSVs, wiring layers, and contacts are tested by testing for conductivity between contacts of the second contact array.

摘要翻译： 提供了一种测试TSV的方法。 在半导体衬底中形成多个TSV。 布线层和第一接触阵列形成在基板的正面上。 布线层将每个TSV耦合到第一接触阵列的相应触头。 导电胶粘剂沉积在第一接触阵列上。 导电粘合剂电耦合第一接触阵列的触点。 载体用导电粘合剂粘合到基底的正面。 在将载体接合到基板之后，将基板的背面变薄以使基板的背面上的每个TSV露出。 形成第二接触阵列，其具有耦合到每个相应TSV的接触。 通过测试第二接触阵列的触头之间的电导率来测试TSV，布线层和触点的电导率和连接。