公开(公告)号：US20050230271A1

公开(公告)日：2005-10-20

申请号：US11033046

申请日：2005-01-11

申请人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

发明人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

IPC分类号： G01N27/26 ,  G01N27/414

CPC分类号： G01N27/4145 ,  G01N27/4148

摘要： Specific ionic interactions with a sensing material that is electrically coupled with the floating gate of a floating gate-based ion sensitive field effect transistor (FGISFET) may be used to sense a target material. For example, an FGISFET can use (e.g., previously demonstrated) ionic interaction-based sensing techniques with the floating gate of floating gate field effect transistors. The floating gate can serves as a probe and an interface to convert chemical and/or biological signals to electrical signals, which can be measured by monitoring the change in the device's threshold voltage, VT.

摘要翻译： 可以使用与浮置栅极离子敏感场效应晶体管（FGISFET）的浮动栅极电耦合的感测材料的特定离子相互作用来感测目标材料。 例如，FGISFET可以使用浮动栅极场效应晶体管的浮动栅极（例如，先前证明的）基于离子相互作用的感测技术。 浮动栅极可以用作探针和将化学和/或生物信号转换成电信号的接口，这可以通过监测器件的阈值电压V T T的变化来测量。

公开(公告)号：US20090108831A1

公开(公告)日：2009-04-30

申请号：US12328893

申请日：2008-12-05

申请人： Kalle LEVON ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

发明人： Kalle LEVON ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

IPC分类号： G01N27/00

CPC分类号： G01N27/4145 ,  G01N27/4148

摘要： Specific ionic interactions with a sensing material that is electrically coupled with the floating gate of a floating gate-based ion sensitive field effect transistor (FGISFET) may be used to sense a target material. For example, an FGISFET can use (e.g., previously demonstrated) ionic interaction-based sensing techniques with the floating gate of floating gate field effect transistors. The floating gate can serves as a probe and an interface to convert chemical and/or biological signals to electrical signals, which can be measured by monitoring the change in the device's threshold voltage, VT.

摘要翻译： 可以使用与浮置栅极离子敏感场效应晶体管（FGISFET）的浮动栅极电耦合的感测材料的特定离子相互作用来感测目标材料。 例如，FGISFET可以使用浮动栅极场效应晶体管的浮动栅极（例如，先前证明的）基于离子相互作用的感测技术。 浮动栅极可以用作探测器和将化学和/或生物信号转换为电信号的接口，这可以通过监测器件的阈值电压VT的变化来测量。

公开(公告)号：US07884398B2

公开(公告)日：2011-02-08

申请号：US12328893

申请日：2008-12-05

申请人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

发明人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

IPC分类号： H01L27/148

CPC分类号： G01N27/4145 ,  G01N27/4148

摘要： Specific ionic interactions with a sensing material that is electrically coupled with the floating gate of a floating gate-based ion sensitive field effect transistor (FGISFET) may be used to sense a target material. For example, an FGISFET can use (e.g., previously demonstrated) ionic interaction-based sensing techniques with the floating gate of floating gate field effect transistors. The floating gate can serves as a probe and an interface to convert chemical and/or biological signals to electrical signals, which can be measured by monitoring the change in the device's threshold voltage, VT.

摘要翻译： 可以使用与浮置栅极离子敏感场效应晶体管（FGISFET）的浮动栅极电耦合的感测材料的特定离子相互作用来感测目标材料。 例如，FGISFET可以使用浮动栅极场效应晶体管的浮动栅极（例如，先前证明的）基于离子相互作用的感测技术。 浮动栅极可以用作探测器和将化学和/或生物信号转换为电信号的接口，这可以通过监测器件的阈值电压VT的变化来测量。

公开(公告)号：US10132773B2

公开(公告)日：2018-11-20

申请号：US12328888

申请日：2008-12-05

申请人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

发明人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

IPC分类号： G01N27/414

摘要： Specific ionic interactions with a sensing material that is electrically coupled with the floating gate of a floating gate-based ion sensitive field effect transistor (FGISFET) may be used to sense a target material. For example, an FGISFET can use (e.g., previously demonstrated) ionic interaction-based sensing techniques with the floating gate of floating gate field effect transistors. The floating gate can serves as a probe and an interface to convert chemical and/or biological signals to electrical signals, which can be measured by monitoring the change in the device's threshold voltage, VT.

公开(公告)号：US20090079414A1

公开(公告)日：2009-03-26

申请号：US12328888

申请日：2008-12-05

申请人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

发明人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

IPC分类号： G01R27/00

CPC分类号： G01N27/4145 ,  G01N27/4148

摘要： Specific ionic interactions with a sensing material that is electrically coupled with the floating gate of a floating gate-based ion sensitive field effect transistor (FGISFET) may be used to sense a target material. For example, an FGISFET can use (e.g., previously demonstrated) ionic interaction-based sensing techniques with the floating gate of floating gate field effect transistors. The floating gate can serves as a probe and an interface to convert chemical and/or biological signals to electrical signals, which can be measured by monitoring the change in the device's threshold voltage, VT.

摘要翻译： 可以使用与浮置栅极离子敏感场效应晶体管（FGISFET）的浮动栅极电耦合的感测材料的特定离子相互作用来感测目标材料。 例如，FGISFET可以使用浮动栅极场效应晶体管的浮动栅极（例如，先前证明的）基于离子相互作用的感测技术。 浮动栅极可以用作探测器和将化学和/或生物信号转换为电信号的接口，这可以通过监测器件的阈值电压VT的变化来测量。

公开(公告)号：US07462512B2

公开(公告)日：2008-12-09

申请号：US11033046

申请日：2005-01-11

申请人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

发明人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

IPC分类号： H01L21/00

CPC分类号： G01N27/4145 ,  G01N27/4148

摘要： Specific ionic interactions with a sensing material that is electrically coupled with the floating gate of a floating gate-based ion sensitive field effect transistor (FGISFET) may be used to sense a target material. For example, an FGISFET can use (e.g., previously demonstrated) ionic interaction-based sensing techniques with the floating gate of floating gate field effect transistors. The floating gate can serves as a probe and an interface to convert chemical and/or biological signals to electrical signals, which can be measured by monitoring the change in the device's threshold voltage, VT.

摘要翻译： 可以使用与浮置栅极离子敏感场效应晶体管（FGISFET）的浮动栅极电耦合的感测材料的特定离子相互作用来感测目标材料。 例如，FGISFET可以使用浮动栅极场效应晶体管的浮动栅极（例如，先前证明的）基于离子相互作用的感测技术。 浮动栅极可以用作探测器和将化学和/或生物信号转换为电信号的接口，这可以通过监测器件的阈值电压VT的变化来测量。

公开(公告)号：US09330823B1

公开(公告)日：2016-05-03

申请号：US13329832

申请日：2011-12-19

申请人： Arifur Rahman ,  Zhaoyin D. Wu ,  Namhoon Kim

发明人： Arifur Rahman ,  Zhaoyin D. Wu ,  Namhoon Kim

IPC分类号： H01F5/00 ,  H01F27/28 ,  H01L27/08

CPC分类号： H01F5/00 ,  H01F17/0006 ,  H01F2017/0073 ,  H01L23/645 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

摘要： An integrated circuit structure can include an interposer having a plurality of conductive layers and a die coupled to the interposer through an internal interconnect structure. The integrated circuit structure can include an inductor implemented within at least one of the conductive layers of the interposer. The inductor can include a first terminal and a second terminal. The first terminal and the second terminal can be coupled to the internal interconnect structure.

摘要翻译： 集成电路结构可以包括具有多个导电层的插入器和通过内部互连结构耦合到插入器的管芯。 集成电路结构可以包括实现在插入器的至少一个导电层内的电感器。 电感器可以包括第一端子和第二端子。 第一端子和第二端子可以耦合到内部互连结构。

公开(公告)号：US08648615B2

公开(公告)日：2014-02-11

申请号：US12824536

申请日：2010-06-28

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： G01R31/20

CPC分类号： G01R31/318513 ,  G01R31/2853 ,  H01L22/14 ,  H01L22/20 ,  H01L22/22 ,  H01L22/32 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157

摘要： A method of testing a multi-die integrated circuit (IC) can include testing an inter-die connection of the multi-die IC. The inter-die connection can include a micro-bump coupling a first die to a second die. The method can include detecting whether a fault occurs during testing of the inter-die connection. Responsive to detecting the fault, the multi-die integrated circuit can be designated as including a faulty inter-die connection. Also described is an integrated circuit that includes a first die, a second die on which the first die may be disposed, a plurality of inter-die connections coupling the first die to the second die, and a plurality of probe pads, where each probe pad is coupled to at least one of the inter-die connections.

摘要翻译： 测试多芯片集成电路（IC）的方法可以包括测试多芯片IC的管芯间连接。 管芯间连接可以包括将第一管芯耦合到第二管芯的微突起。 该方法可以包括在芯片间连接的测试期间检测故障是否发生。 响应于检测故障，多芯片集成电路可以被指定为包括故障的管芯间连接。 还描述了一种集成电路，其包括第一管芯，可以设置第一管芯的第二管芯，将第一管芯耦合到第二管芯的多个管芯间连接，以及多个探针焊盘，其中每个探针 焊盘耦合到至少一个管芯间连接。

公开(公告)号：US08332803B1

公开(公告)日：2012-12-11

申请号：US12824542

申请日：2010-06-28

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5018 ,  G06F2217/76 ,  G06F2217/80

摘要： A method and apparatus for integrated circuit package thermo-mechanical reliability analysis are described. In some examples, a computer-implemented method of modeling stress in a packaged semiconductor device includes: selecting, using a computer, successive portions of a package layout for the semiconductor device, each of the successive portions of the package layout describing physical layout of at least one interconnect structure in the semiconductor device; for each portion of the successive portions of the package layout: (1) selecting a pre-defined layout from a library of pre-defined layouts based on the portion of the package layout; (2) obtaining pre-characterization information for the pre-defined layout that defines structural properties of the pre-defined layout; and (3) executing a modeling algorithm to determine a stress measurement for the portion of the package layout using the pre-characterization information as parametric input; and combining stress measurements for each of the successive portions of the package layout to determine a stress profile for the semiconductor device.

摘要翻译： 描述了用于集成电路封装热机械可靠性分析的方法和装置。 在一些示例中，计算机实现的封装半导体器件中的应力建模方法包括：使用计算机选择用于半导体器件的封装布局的连续部分，封装布局的每个连续部分描述物理布局 半导体器件中的至少一个互连结构; 对于包装布局的连续部分的每个部分：（1）基于包装布局的部分从预定义布局的库中选择预定义的布局; （2）获得预定义布局的预定义信息，该预定义布局定义预定义布局的结构特性; 和（3）执行建模算法以使用预表征信息作为参数输入来确定包装布局的部分的应力测量; 以及将包装布局的每个连续部分的应力测量结合以确定半导体器件的应力分布。

公开(公告)号：US08179159B1

公开(公告)日：2012-05-15

申请号：US13116276

申请日：2011-05-26

申请人： Stephen M. Trimberger ,  Arifur Rahman

发明人： Stephen M. Trimberger ,  Arifur Rahman

IPC分类号： H03K19/173 ,  G06F7/38

CPC分类号： H03K19/17736

摘要： A method of configuring a stacked integrated circuit (“IC”) having a first IC die with configurable logic and a second IC die electrically coupled to the first IC die through an array of inter-chip contacts includes: providing a frame having frame data and a frame address in a frame header to the first IC die; storing the frame data in a frame data register of the first IC die; processing the frame header to determine whether a frame destination is in the first IC die or the second IC die; in response to determining that the frame destination is in the second IC die, providing the frame address to the second IC die through an inter-chip frame address bus including a first plurality of the array of inter-chip contacts; and writing the frame data from the frame data register of the first IC die to the frame destination through an inter-chip frame data bus including a second plurality of the array of inter-chip contacts.

摘要翻译： 一种配置具有可配置逻辑的第一IC芯片的堆叠集成电路（“IC”）和通过芯片间触点阵列电耦合到第一IC裸片的第二IC裸片的方法包括：提供具有帧数据的帧和 第一IC芯片的帧头中的帧地址; 将帧数据存储在第一IC芯片的帧数据寄存器中; 处理帧头以确定帧目的地是否在第一IC管芯或第二IC管芯中; 响应于确定帧目的地在第二IC芯片中，通过包括第一多个芯片间接触阵列的片间帧地址总线将第二IC芯片提供帧地址; 以及通过包括第二多个芯片间接触阵列的片间帧数据总线将帧数据从第一IC芯片的帧数据寄存器写入帧目的地。