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    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
    41.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF 有权

    公开(公告)号：US20220238679A1

    公开(公告)日：2022-07-28

    申请号：US17527857

    申请日：2021-11-16

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Te-Hsin Chiu ,  Shih-Wei Peng ,  Wei-An Lai ,  Jiann-Tyng Tzeng

    IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L23/48

    摘要： A semiconductor device and a method of manufacturing the device are disclosed. In one aspect, the semiconductor device includes a first active region that extends along a first lateral direction and includes a plurality of first epitaxial structures. The semiconductor device also includes an interconnect structure that also extends along the first lateral direction and is disposed below the first active region, wherein at least one of the plurality of first epitaxial structures is electrically coupled to the interconnect structure. The interconnect structure includes at least a first portion that offsets from the first active region along a second lateral direction perpendicular to the first lateral direction.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
    42.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF 有权

    公开(公告)号：US20220238371A1

    公开(公告)日：2022-07-28

    申请号：US17533000

    申请日：2021-11-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Te-Hsin Chiu ,  Shih-Wei Peng ,  Wei-An Lai ,  Jiann-Tyng Tzeng

    IPC分类号： H01L21/762 ,  H01L21/66 ,  H01L21/74 ,  H01L21/3115

    摘要： A method includes: doping a region through a first surface of a semiconductor substrate; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors comprises one or more source/drain structures electrically coupled to the doped region through a corresponding one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting signals present on the doped region through a second surface of the semiconductor substrate, the second surface opposite to the first surface.

    Method of manufacturing a semiconductor device, and associated semiconductor device and system
    43.
    发明授权
    Method of manufacturing a semiconductor device, and associated semiconductor device and system 有权

    公开(公告)号：US11257670B2

    公开(公告)日：2022-02-22

    申请号：US16786418

    申请日：2020-02-10

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： Shih-Wei Peng ,  Chia-Tien Wu ,  Jiann-Tyng Tzeng

    IPC分类号： H01L23/58 ,  H01L21/02 ,  H01L21/033

    摘要： A method of manufacturing a semiconductor device, including: providing a substrate including a first cell and a second cell that are arranged in a first direction; forming a plurality of first metal strips extending in the first direction and arranged in a second direction on a first plane; forming a first trench over a boundary between the first cell and the second cell, wherein a bottom surface of the first trench is on a second plane over the first plane; filling the first trench with a non-conductive material, resulting in a separating wall which extends in the first direction; and forming a plurality of second metal strips extending in the second direction on a third plane over the second plane, wherein a first second metal strip and a second second metal strip separated from each other by the separating wall; wherein the second direction is orthogonal to the first direction.

    Semiconductor structure, device, and method
    46.
    发明授权
    Semiconductor structure, device, and method 有权

    公开(公告)号：US10977417B2

    公开(公告)日：2021-04-13

    申请号：US16571809

    申请日：2019-09-16

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Shih-Wei Peng ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin

    IPC分类号： G06F17/50 ,  G06F30/398 ,  G03F1/70 ,  G03F1/36

    摘要： A structure includes first, second, third, and fourth conductive segments, and a gate. The first and second conductive segments are in a first conductive layer and configured as first and second terminals of a first transistor of a first type. The third and fourth conductive segments are in a second conductive layer stacked over the first conductive layer and configured as first and second terminals of a second transistor of a second type. The first gate is arranged, in a first direction, between the first and third conductive segments and the second and fourth conductive segments. The gate is configured as a control terminal of the first transistor and a control terminal of the second transistor, the first conductive segment is offset from the third conductive segment along the first direction, and the second conductive segment is offset from the fourth conductive segment along the first direction.

    Circuit layout
    48.
    发明授权
    Circuit layout 有权

    公开(公告)号：US12039246B2

    公开(公告)日：2024-07-16

    申请号：US18325501

    申请日：2023-05-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Shih-Wei Peng ,  Kam-Tou Sio ,  Jiann-Tyng Tzeng

    IPC分类号： G06F30/392 ,  G06F30/394 ,  G06F30/396

    CPC分类号： G06F30/392 ,  G06F30/394 ,  G06F30/396

    摘要： Generating a circuit layout is provided. A circuit layout associated with a circuit is received. A parallel pattern recognition is performed on the circuit layout. Performing the parallel pattern recognition includes determining that there is a parallel pattern in the circuit layout. In response to determining that there is a parallel pattern in the circuit layout, a cell swap for a first cell associated with the parallel pattern with a second cell is performed. After the cell swap for the first cell, engineering change order routing is performed to connect the second cell in the circuit layout. An updated circuit layout having the second cell is provided.

    Cell structures and power routing for integrated circuits
    50.
    发明授权
    Cell structures and power routing for integrated circuits 有权

    公开(公告)号：US11908538B2

    公开(公告)日：2024-02-20

    申请号：US17127091

    申请日：2020-12-18

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Shih-Wei Peng ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio

    IPC分类号： G11C5/14 ,  G11C5/06 ,  H01L23/538 ,  H01L23/50

    CPC分类号： G11C5/14 ,  G11C5/06 ,  H01L23/50 ,  H01L23/5386

    摘要： Various memory cell structures and power routings for one or more cells in an integrated circuit are disclosed. In one embodiment, different metal layers are used for power stripes that are operable to connect to voltage sources to supply different voltage signals, which allows some or all of the power stripes to have a larger width. Additionally or alternatively, fewer metal stripes are used for signals in a metal layer to allow the power stripe in that metal layer to have a larger width. The larger width(s) in turn increases the total area of the power stripe(s) to reduce the IR drop across the power stripe. The various power routings include connecting metal pillars in one metal layer to a power stripe in another metal layer, and extending a metal stripe in one metal layer to provide additional connections to a power stripe in another metal layer.