公开(公告)号：US20160181979A1

公开(公告)日：2016-06-23

申请号：US14579404

申请日：2014-12-22

申请人： Opel Solar, Inc. ,  The University of Connecticut

发明人： Geoff W. Taylor

IPC分类号： H03B17/00 ,  H03K17/78 ,  H03K17/687 ,  H04B10/63

CPC分类号： H03B17/00 ,  G02B6/42 ,  H01L31/1113 ,  H01L31/1129 ,  H03K17/687 ,  H03K17/78 ,  H04B10/63

摘要： An optoelectronic circuit for producing an optical clock signal that includes an optical thyristor, a waveguide structure and control circuitry. The waveguide structure is configured to split an optical pulse produced by the optical thyristor such that a first portion of such optical pulse is output as part of the optical clock signal and a second portion of such optical pulse is guided back to the optical thyristor to produce another optical pulse that is output as part of the optical clock signal. The control circuitry is operably coupled to terminals of the optical thyristor and receives first and second control signal inputs. The control circuitry is configured to selectively decrease frequency of the optical clock signal based on the first control signal input and to selectively increase frequency of the optical clock signal based on the second control signal input.

摘要翻译： 一种用于产生包含光学晶闸管，波导结构和控制电路的光时钟信号的光电子电路。 波导结构被配置为分离由光晶闸管产生的光脉冲，使得这种光脉冲的第一部分作为光时钟信号的一部分输出，并且这种光脉冲的第二部分被引导回到光晶闸管以产生 作为光时钟信号的一部分输出的另一个光脉冲。 控制电路可操作地耦合到光晶闸管的端子并且接收第一和第二控制信号输入。 控制电路被配置为基于第一控制信号输入选择性地降低光时钟信号的频率，并且基于第二控制信号输入选择性地增加光时钟信号的频率。

公开(公告)号：US20160178988A1

公开(公告)日：2016-06-23

申请号：US14578950

申请日：2014-12-22

申请人： Opel Solar, Inc. ,  The University of Connecticut

发明人： Geoff W. Taylor

IPC分类号： G02F3/00

CPC分类号： G06E1/00 ,  G02F3/00 ,  G11C13/04 ,  H03K3/42 ,  H03K19/14 ,  H04B10/63

摘要： An optical AND gate is provided that includes an optical thyristor configured to receive first and second digital optical signal inputs. The optical AND gate further includes control circuitry operably coupled to terminals of said optical thyristor. The control circuitry is configured to control switching operation of said optical thyristor in response to the ON/OFF states of the first and second digital optical signal inputs such that the optical thyristor produces a digital output signal that represents the AND function of the first and second digital optical signal inputs.In another aspect, an AND gate is provided that includes a thyristor and control circuitry operably coupled to terminals of the thyristor. The control circuitry is configured to receive first and second digital electrical signal inputs and control switching operation of the thyristor in response to the levels of the first and second digital electrical signal inputs such that the thyristor produces a digital output signal that represents the AND function of the first and second digital electrical signal inputs.

摘要翻译： 提供了一种光学AND门，其包括被配置为接收第一和第二数字光信号输入的光学晶闸管。 光学与门还包括可操作地耦合到所述光晶闸管的端子的控制电路。 控制电路被配置为响应于第一和第二数字光信号输入的ON / OFF状态来控制所述光晶闸管的开关操作，使得光晶闸管产生表示第一和第二数字光信号输入的AND功能的数字输出信号 数字光信号输入。 在另一方面，提供了与门，其包括可操作地耦合到晶闸管的端子的晶闸管和控制电路。 控制电路被配置为响应于第一和第二数字电信号输入的电平而接收第一和第二数字电信号输入并且控制晶闸管的开关操作，使得晶闸管产生表示的功能的数字输出信号 第一和第二数字电信号输入。

公开(公告)号：US09281059B2

公开(公告)日：2016-03-08

申请号：US14609064

申请日：2015-01-29

申请人： Opel Solar, Inc. ,  The University of Connecticut

发明人： Geoff W. Taylor

IPC分类号： G11C11/34 ,  G11C13/00 ,  G11C11/39 ,  G11C14/00 ,  H01L27/24 ,  H01L45/00

CPC分类号： G11C13/0004 ,  G11C11/39 ,  G11C13/0097 ,  G11C14/0045 ,  G11C14/009 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

摘要： A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row of the array is formed on the substrate and coupled to MC current paths for the corresponding row. Bit lines corresponding to respective columns of the array are formed on the substrate and can be coupled to a modulation doped QW interface of the MC thyristors for the corresponding column. Circuitry is configured to apply an electrical signal to the word line(s) in order to generate current that programs phase change material of the MC load elements into one of a high or low resistive state according to state of the current path of the MCs for non-volatile backup purposes.

公开(公告)号：US20160025926A1

公开(公告)日：2016-01-28

申请号：US14444629

申请日：2014-07-28

申请人： The University of Connecticut ,  Opel Solar, Inc.

发明人： Geoff W. Taylor

IPC分类号： G02B6/122 ,  G02B6/34 ,  G02B6/42 ,  H01P3/02

CPC分类号： G02B6/29343 ,  G02B6/12007 ,  G02B6/122 ,  G02B6/124 ,  G02B6/29338 ,  G02B6/2938 ,  G02B6/29395 ,  G02B6/34 ,  G02B6/4274 ,  G02B2006/12104 ,  G02F1/011 ,  G02F2203/15 ,  H01P3/003 ,  H01P3/026 ,  H01S5/026 ,  H01S5/1032 ,  H01S5/125 ,  H01S5/4025 ,  H01S5/4087

摘要： A WDM transmitter and/or receiver optoelectronic integrated circuit includes a plurality of microresonators and corresponding waveguides and couplers that are integrally formed on a substrate. For the WDM transmitter, the microresonators and waveguides are configured to generate a plurality of optical signals at different wavelengths. Each coupler includes a resonant cavity waveguide that is configured to transmit one optical signal from one waveguide to the output waveguide such that the plurality of optical signals are multiplexed on the output waveguide. For the WDM receiver, an input waveguide is configured to provide for propagation of a plurality of optical signals at different wavelengths. Each coupler includes a resonant cavity waveguide that is configured to transmit at least one optical signal from the input waveguide to one waveguide. The waveguides and microresonators are configured to perform optical-to-electrical conversion of the plurality of optical signals at different wavelengths that propagate in the waveguides.

摘要翻译： WDM发射器和/或接收器光电集成电路包括多个微谐振器和一体地形成在衬底上的对应的波导管和耦合器。 对于WDM发射机，微谐振器和波导被配置为产生不同波长的多个光信号。 每个耦合器包括谐振腔波导，其被配置为将一个光信号从一个波导传输到输出波导，使得多个光信号被多路复用在输出波导上。 对于WDM接收机，输入波导被配置为提供不同波长的多个光信号的传播。 每个耦合器包括谐振腔波导，其被配置为将至少一个光信号从输入波导传输到一个波导。 波导和微谐振器被配置为对在波导中传播的不同波长的多个光信号进行光电转换。

公开(公告)号：US20150138881A1

公开(公告)日：2015-05-21

申请号：US14609064

申请日：2015-01-29

申请人： Opel Solar, Inc. ,  The University of Connecticut

发明人： Geoff W. Taylor

IPC分类号： G11C13/00

CPC分类号： G11C13/0004 ,  G11C11/39 ,  G11C13/0097 ,  G11C14/0045 ,  G11C14/009 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

摘要： A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row of the array is formed on the substrate and coupled to MC current paths for the corresponding row. Bit lines corresponding to respective columns of the array are formed on the substrate and can be coupled to a modulation doped QW interface of the MC thyristors for the corresponding column. Circuitry is configured to apply an electrical signal to the word line(s) in order to generate current that programs phase change material of the MC load elements into one of a high or low resistive state according to state of the current path of the MCs for non-volatile backup purposes.

摘要翻译： 一种半导体存储器件，包括形成在衬底上的存储器单元阵列，每个存储单元由负载元件和晶闸管实现，所述晶闸管的状态表示由MC存储的易失性位值的可切换电流通路。 在衬底上形成对应于阵列的相应行的至少一个字线，并耦合到用于相应行的MC电流路径。 对应于阵列的各列的位线形成在衬底上，并且可以耦合到相应列的MC晶闸管的调制掺杂QW接口。 电路被配置为向字线施加电信号，以便产生根据MC的当前路径的状态来编程将MC负载元件的材料相变成高电阻或低电阻状态的电流， 非易失性备份的目的。