公开(公告)号：US20210328059A1

公开(公告)日：2021-10-21

申请号：US17023125

申请日：2020-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/10

Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.

公开(公告)号：US20210202385A1

公开(公告)日：2021-07-01

申请号：US16947390

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Cheng-Ting Chung ,  Cheng-Chi Chuang ,  Shang-Wen Chang

IPC: H01L23/528 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source/drain feature formed on the active region and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; and a backside contact feature interposed between the backside power rail and the first source/drain feature, and electrically connecting the backside power rail to the first source/drain feature. The backside contact feature further includes a first silicide layer on the back side of the substrate.

公开(公告)号：US20210098634A1

公开(公告)日：2021-04-01

申请号：US16583449

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a fin substrate having a first dopant concentration; an anti-punch through (APT) layer disposed over the fin substrate, wherein the APT layer has a second dopant concentration that is greater than the first dopant concentration; a nanostructure including semiconductor layers disposed over the APT layer; a gate structure disposed over the nanostructure and wrapping each of the semiconductor layers, wherein the gate structure includes a gate dielectric and a gate electrode; a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature disposed over the APT layer, wherein the gate structure is disposed between the first epitaxial S/D feature and the second epitaxial S/D feature; and an isolation layer disposed between the APT layer and the fin substrate, wherein a material of the isolation layer is the same as a material of the gate dielectric.

公开(公告)号：US20210098588A1

公开(公告)日：2021-04-01

申请号：US16583485

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Yi-Bo Liao ,  Hou-Yu Chen ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L29/40 ,  H01L21/321 ,  H01L21/311 ,  H01L29/08

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.

公开(公告)号：US20250159971A1

公开(公告)日：2025-05-15

申请号：US19027595

申请日：2025-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H10D84/03 ,  H10D64/01 ,  H10D84/01 ,  H10D84/83

Abstract: A semiconductor device includes a substrate having a fin element extending therefrom. In some embodiments, a gate structure is formed over the fin element, where the gate structure includes a dielectric layer on the fin element, a metal capping layer disposed over the dielectric layer, and a metal electrode formed over the metal capping layer. In some cases, first sidewall spacers are formed on opposing sidewalls of the metal capping layer and the metal electrode. In various embodiments, the dielectric layer extends laterally underneath the first sidewall spacers to form a dielectric footing region.

公开(公告)号：US12205848B2

公开(公告)日：2025-01-21

申请号：US17568114

申请日：2022-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device includes a substrate having a fin element extending therefrom. In some embodiments, a gate structure is formed over the fin element, where the gate structure includes a dielectric layer on the fin element, a metal capping layer disposed over the dielectric layer, and a metal electrode formed over the metal capping layer. In some cases, first sidewall spacers are formed on opposing sidewalls of the metal capping layer and the metal electrode. In various embodiments, the dielectric layer extends laterally underneath the first sidewall spacers to form a dielectric footing region.

公开(公告)号：US12009293B2

公开(公告)日：2024-06-11

申请号：US17693925

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Cheng-Ting Chung ,  Wei Ju Lee

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7685 ,  H01L21/76877

Abstract: Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.

公开(公告)号：US11862701B2

公开(公告)日：2024-01-02

申请号：US17332715

申请日：2021-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Hou-Yu Chen ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device according to the present disclosure includes a stack of first channel layers and first and second source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively. The first and second S/D epitaxial features have a first conductivity type. The semiconductor device also includes a stack of second channel layers stacked over the first channel layers and third and fourth source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the second channel layers, respectively. The third and fourth S/D epitaxial features have a second conductivity type. A total active channel layer number of the first channel layers is different from that of the second channel layers.

公开(公告)号：US11837538B2

公开(公告)日：2023-12-05

申请号：US17723116

申请日：2022-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Wei Ju Lee ,  Cheng-Ting Chung ,  Hou-Yu Chen ,  Chun-Fu Cheng ,  Kuan-Lun Cheng

IPC: H01L23/522 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.

公开(公告)号：US11777033B2

公开(公告)日：2023-10-03

申请号：US17133290

申请日：2020-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wang ,  Chun-Hsiung Lin ,  Cheng-Ting Chung ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/66795

Abstract: A semiconductor device according to the present disclosure includes a first isolation feature and a second isolation feature, a fin structure extending lengthwise along a first direction and sandwiched between the first isolation feature and the second isolation feature along a second direction perpendicular to the first direction, a first channel member disposed over the first isolation feature, a second channel member disposed over the second isolation feature, and a gate structure disposed over and wrapping around the first channel member and the second channel member.