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    Integrated ESD Protection Circuit for GaN Based Device
    42.
    发明申请
    Integrated ESD Protection Circuit for GaN Based Device 审中-公开

    公开(公告)号：US20180026029A1

    公开(公告)日：2018-01-25

    申请号：US15215651

    申请日：2016-07-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Syuan Lin ,  Ming-Cheng Lin ,  King-Yuen Wong ,  Jiun-Lei Yu ,  Chun Lin Tsai

    IPC: H01L27/02 ,  H01L49/02 ,  H01L27/06 ,  H01L29/20 ,  H01L29/778

    CPC classification number: H01L28/20 ,  H01L27/0248 ,  H01L27/0605

    Abstract: The present disclosure relates to an electrostatic discharge (ESD) protection circuit integrated with a gallium nitride (GaN) based transistor and configured to clamp a gate input voltage of the gallium nitride (GaN) based transistor during an ESD surge event, and associated methods. In some embodiments, the ESD protection circuit includes a first ESD protection stage and a second ESD protection stage connected between a gate terminal and a source terminal of the GaN based transistor. The first ESD protection stage includes a first plurality of GaN based gate-to-source shorted transistors connected in series and further connected to a first terminal of a first resistor. The second ESD protection stage is connected to the first ESD protection stage in parallel. The second ESD protection stage comprises a first GaN based shunt transistor having a gate terminal connected to the first terminal of the first resistor.

    SERIES RESISTOR OVER DRAIN REGION IN HIGH VOLTAGE DEVICE
    43.
    发明申请
    SERIES RESISTOR OVER DRAIN REGION IN HIGH VOLTAGE DEVICE 有权
    系列电阻在高压设备中的漏电区域

    公开(公告)号：US20150262995A1

    公开(公告)日：2015-09-17

    申请号：US14208791

    申请日：2014-03-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

    IPC: H01L27/02 ,  H01L23/522 ,  H01L49/02 ,  H01L27/06 ,  H01L21/8234

    CPC classification number: H01L27/0288 ,  H01L21/823475 ,  H01L23/5228 ,  H01L27/0629 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a drain region and a channel region surrounding the drain region. A source region surrounds the channel region such that the channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and has an inner edge proximate to the drain. A resistor structure, which is made up of a curved or polygonal path of resistive material, is arranged over the drain and is coupled to the drain. The resistor structure is perimeterally bounded by the inner edge of the gate electrode.

    Abstract translation: 一些实施例涉及半导体器件。 半导体器件包括漏极区域和围绕漏极区域的沟道区域。 源极区域围绕沟道区域，使得沟道区域将漏极区域与源极区域分离。 栅极电极布置在沟道区域的上方，并且具有靠近漏极的内边缘。 由电阻材料的弯曲或多边形路径构成的电阻器结构布置在漏极上并且耦合到漏极。 电阻器结构由栅电极的内边缘周边界定。

    OHMIC ELECTRODE FOR TWO-DIMENSIONAL CARRIER GAS (2DCG) SEMICONDUCTOR DEVICE
    47.
    发明申请
    OHMIC ELECTRODE FOR TWO-DIMENSIONAL CARRIER GAS (2DCG) SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220336600A1

    公开(公告)日：2022-10-20

    申请号：US17353051

    申请日：2021-06-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Chien Liu ,  Yao-Chung Chang ,  Chun Lin Tsai

    IPC: H01L29/417 ,  H01L29/778 ,  H01L29/66 ,  H01L29/40

    Abstract: Various embodiments of the present disclosure are directed towards a two-dimensional carrier gas (2DCG) semiconductor device comprising an ohmic source/drain electrode with a plurality of protrusions separated by gaps and protruding from a bottom surface of the ohmic source/drain electrode. The ohmic source/drain electrode overlies a semiconductor film, and the protrusions extend from the bottom surface into the semiconductor film. Further, the ohmic source/drain electrode is separated from another ohmic source/drain electrode that also overlies the semiconductor film. The semiconductor film comprises a channel layer and a barrier layer that are vertically stacked and directly contact at a heterojunction. The channel layer accommodates a 2DCG that extends along the heterojunction and is ohmically coupled to the ohmic source/drain electrode and the other ohmic source/drain electrode. A gate electrode overlies the semiconductor film between the ohmic source/drain electrode and the other source/drain electrode.

    ELECTRODE STRUCTURE FOR VERTICAL GROUP III-V DEVICE
    48.
    发明申请
    ELECTRODE STRUCTURE FOR VERTICAL GROUP III-V DEVICE 有权

    公开(公告)号：US20210376090A1

    公开(公告)日：2021-12-02

    申请号：US16884292

    申请日：2020-05-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yao-Chung Chang ,  Chun Lin Tsai ,  Ru-Yi Su ,  Wei Wang ,  Wei-Chen Yang

    IPC: H01L29/417 ,  H01L29/66

    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a buffer layer disposed between an active layer and a substrate. The active layer overlies the substrate. The substrate and the buffer layer include a plurality of pillar structures that extend vertically from a bottom surface of the active layer in a direction away from the active layer. A top electrode overlies an upper surface of the active layer. A bottom electrode underlies the substrate. The bottom electrode includes a conductive body and a plurality of conductive structures that respectively extend continuously from the conductive body, along sidewalls of the pillar structures, to a lower surface of the active layer.

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