公开(公告)号：US20200035672A1

公开(公告)日：2020-01-30

申请号：US16578299

申请日：2019-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Dun-Nian Yaung ,  Fu-Jier Fan ,  Hsing-Chih Lin ,  Hsiao-Chin Tuan ,  Jen-Cheng Liu ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC: H01L27/06 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L23/522 ,  H01L23/48

Abstract: A three-dimensional (3D) integrated circuit (IC) and associated forming method are provided. In some embodiments, a second IC die is bonded to a first IC die through a second bonding structure and a first bonding structure at a bonding interface. The bonding encloses a seal-ring structure in a peripheral region of the 3D IC in the first and second IC dies. The seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. The bonding forms a plurality of through silicon via (TSV) coupling structures at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure by electrically and correspondingly connects a first plurality of TSV wiring layers and inter-wire vias and a second plurality of TSV wiring layers and inter-wire vias.

公开(公告)号：US09502556B2

公开(公告)日：2016-11-22

申请号：US14321508

申请日：2014-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Chi Wu ,  Yu-Lung Yeh ,  Chieh-Shuo Liang ,  Shih-Chang Lin ,  Meng-Yi Wu ,  Hsing-Chih Lin

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/66 ,  H01L49/02 ,  H01L29/8605 ,  H01L21/8234

CPC classification number: H01L29/7833 ,  H01L21/823462 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/66166 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/8605

Abstract: In a method for manufacturing a semiconductor device, a substrate including a gate structure is provided. A source region and a drain region are formed at opposing sides of the gate structure and an implant region for a resistor device is formed in the substrate. Pocket implant regions are formed in the source region and the drain region. A dielectric layer is formed to cover the gate structure and the substrate. A portion of dopants in the pocket implant regions interact with portions of dopants in the source region and the drain region to form lightly doped drain regions above the pocket implant regions. A resistor region of the resistor device is defined on the implant region. A portion of the dielectric layer is removed to form a spacer on a sidewall of the gate structure and a resistor protection dielectric layer on a portion of the implant region.

Abstract translation: 在制造半导体器件的方法中，提供了包括栅极结构的衬底。 源极区域和漏极区域形成在栅极结构的相对侧，并且在衬底中形成用于电阻器件的注入区域。 在源极区域和漏极区域中形成袋状注入区域。 形成介电层以覆盖栅极结构和衬底。 口袋注入区域中的一部分掺杂剂与源区域和漏区域中的掺杂剂的部分相互作用以在口袋注入区域上方形成轻掺杂的漏极区域。 电阻器件的电阻器区域被限定在植入区域上。 去除电介质层的一部分以在栅极结构的侧壁上形成间隔物，并在植入区域的一部分上形成电阻器保护电介质层。

公开(公告)号：US09257486B2

公开(公告)日：2016-02-09

申请号：US14204388

申请日：2014-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Hsing-Chih Lin

IPC: H01L29/06 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1675 ,  H01L45/1683

Abstract: An RRAM array is provided. The RRAM array includes a plurality of horizontal electrode lines elongated in a horizontal direction. The RRAM array also includes a plurality of conducting structures elongated in a vertical direction. Each of the conducting structures includes a plurality of electrode blocks and a plurality of contact vias which are alternately arranged. The electrode blocks and the electrode lines are on the same horizontal planes. The RRAM array further includes a plurality of resistance variable elements sandwiched between the electrode lines and the electrode blocks.

Abstract translation: 提供RRAM阵列。 RRAM阵列包括沿水平方向细长的多个水平电极线。 RRAM阵列还包括在垂直方向上伸长的多个导电结构。 每个导电结构包括多个电极块和交替布置的多个接触孔。 电极块和电极线在相同的水平面上。 RRAM阵列还包括夹在电极线和电极块之间的多个电阻可变元件。

公开(公告)号：US09246084B2

公开(公告)日：2016-01-26

申请号：US14162024

申请日：2014-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Chih Lin

IPC: H01L47/00 ,  H01L45/00 ,  H01L51/05 ,  H01L51/00

CPC classification number: H01L45/1273 ,  H01L45/04 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1616 ,  H01L51/0035 ,  H01L51/0591

Abstract: Embodiments of a resistive random access memory (RRAM) cell structure are provided. The RRAM cell structure includes a first electrode over a substrate. The RRAM cell structure also includes a resistance variable layer over the first electrode. The resistance variable layer has a first portion in a V-shape. The RRAM cell structure further includes a second electrode over the resistance variable layer.

Abstract translation: 提供了电阻随机存取存储器（RRAM）单元结构的实施例。 RRAM单元结构包括在衬底上的第一电极。 RRAM单元结构还包括在第一电极上的电阻变化层。 电阻变化层具有V形的第一部分。 RRAM单元结构还包括位于电阻变化层上的第二电极。

公开(公告)号：US20240355815A1

公开(公告)日：2024-10-24

申请号：US18763542

申请日：2024-07-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsing-Chih Lin

IPC: H01L27/06 ,  H01L21/265 ,  H01L23/00 ,  H01L23/522 ,  H01L29/66 ,  H01L29/861

CPC classification number: H01L27/0676 ,  H01L21/26513 ,  H01L23/5226 ,  H01L24/08 ,  H01L28/40 ,  H01L29/66136 ,  H01L29/861 ,  H01L2224/08145

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first substrate, a capacitor within the first substrate, a diode structure within the first substrate adjacent the capacitor, and a first interconnect structure over the capacitor and the diode structure. A first conductive via of the first interconnect structure electrically couples the capacitor to the diode structure.

公开(公告)号：US20220223635A1

公开(公告)日：2022-07-14

申请号：US17321909

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsing-Chih Lin ,  Feng-Chi Hung ,  Shyh-Fann Ting

IPC: H01L27/146

Abstract: A semiconductor device includes a substrate having a front side and a back side opposite to each other. A plurality of photodetectors is disposed in the substrate within a pixel region. An isolation structure is disposed within the pixel region and between the photodetectors. The isolation structure includes a back side isolation structure extending from the back side of the substrate to a position in the substrate. A conductive plug structure is disposed in the substrate within a periphery region. A conductive cap is disposed on the back side of the substrate and extends from the pixel region to the periphery region and electrically connects the back side isolation structure to the conductive plug structure. A conductive contact lands on the conductive plug structure, and is electrically connected to the back side isolation structure through the conductive plug structure and the conductive cap.

公开(公告)号：US20220223498A1

公开(公告)日：2022-07-14

申请号：US17144717

申请日：2021-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zheng-Xun Li ,  Min-Feng Kao ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Dun-Nian Yaung

IPC: H01L23/48 ,  H01L21/768

Abstract: Some embodiments relate to a semiconductor structure including a semiconductor substrate, and n interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a dielectric structure and a plurality of metal lines that are stacked over one another in the dielectric structure. A through substrate via (TSV) extends through the semiconductor substrate to contact a metal line of the plurality of metal lines. A protective sleeve is disposed along outer sidewalls of the TSV and separates the outer sidewalls of the TSV from the dielectric structure of the interconnect structure.

公开(公告)号：US20210391302A1

公开(公告)日：2021-12-16

申请号：US16898613

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Yi-Shin Chu ,  Ping-Tzu Chen ,  Che-Wei Chen

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/532 ,  H01L21/768

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

公开(公告)号：US20210391237A1

公开(公告)日：2021-12-16

申请号：US16898647

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Yi-Shin Chu ,  Ping-Tzu Chen

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a standard via disposed on a first side of a substrate. An oversized via is disposed on the first side of the substrate and is laterally separated from the standard via. The oversized via has a larger width than the standard via. An interconnect wire vertically contacting the oversized via. A through-substrate via (TSV) extends from a second side of the substrate, and through the substrate, to physically contact the oversized via or the interconnect wire. The TSV has a minimum width that is smaller than a width of the oversized via.

公开(公告)号：US11195818B2

公开(公告)日：2021-12-07

申请号：US16568623

申请日：2019-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Tzu Chen ,  Hsing-Chih Lin ,  Min-Feng Kao

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/48 ,  H01L27/088 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: In some embodiments, the present disclosure relates to a three dimensional (3D) integrated circuit (IC) stack, including a first IC die having a first substrate and a first interconnect structure over a frontside of the first substrate; a second IC die having a second substrate and a second interconnect structure over the frontside of the second substrate; and a third IC die vertically between the first and second IC dies and having a third substrate, a third interconnect structure over the frontside of the third substrate, and a third bonding structure over a backside of the third substrate. A heat dissipation path extends from the third substrate to at least the first or second substrate, and includes a backside contact that extends from the third bonding structure to the backside of the third substrate and that is thermally coupled to at least the first or second interconnect structure.