公开(公告)号：US20210134677A1

公开(公告)日：2021-05-06

申请号：US16856033

申请日：2020-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Yi-Bo Liao ,  Yi-Ruei Jhan

IPC: H01L21/8234 ,  H01L29/423 ,  H01L21/762

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack.

公开(公告)号：US20210098605A1

公开(公告)日：2021-04-01

申请号：US16583388

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wang ,  Kuo-Cheng Chiang ,  Lo-Heng Chang ,  Jung-Hung Chang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/423 ,  H01L27/11 ,  H01L29/10 ,  H01L29/08 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device according to the present disclosure includes first gate-all-around (GAA) devices in a first device area and a second GAA devices in a second device area. Each of the first GAA devices includes a first vertical stack of channel members, a first gate structure over and around the first vertical stack of channel members, and a plurality of inner spacer features. Each of the second GAA devices includes a second vertical stack of channel members and a second gate structure over and around the second vertical stack of channel members. Two adjacent channel members of the first vertical stack of channel members are separated by a portion of the first gate structure and at least one of the plurality of inner spacer features. Two adjacent channel members of the second vertical stack of channel members are separated only by a portion of the second gate structure.

公开(公告)号：US10943830B2

公开(公告)日：2021-03-09

申请号：US15724411

申请日：2017-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Kuan-Ting Pan

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L27/12 ,  H01L21/84

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures. The present disclosure provides self-aligned isolation fins that can be formed by depositing dielectric material in openings formed in a spacing layer or by replacing portions of fins with dielectric material. The self-aligned isolation fins can be separated from each other by a critical dimension of the utilized photolithography process. The separation between self-aligned isolation fins or between the self-aligned isolation fins and active fins can be approximately equal to or larger than the separations of the active fins.

公开(公告)号：US20200287041A1

公开(公告)日：2020-09-10

申请号：US16883227

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Chi-Wen Liu ,  Ying-Keung Leung

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/417 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/12 ,  H01L27/088 ,  H01L29/06 ,  H01L29/45

Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.

公开(公告)号：US10755983B2

公开(公告)日：2020-08-25

申请号：US16204892

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Kuan-Lun Cheng ,  Yen-Ming Chen

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762

Abstract: A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench isolation (STI) region on the substrate. First and second fin portions of the fin structure extend above a top surface of the STI region. The method further includes oxidizing the first fin portion to convert a first material of the first fin portion to a second material. The second material is different from the first material of the first fin portion and a material of the second fin portion. The method further includes forming an oxide layer on the oxidized first fin portion and the second fin portion and forming first and second polysilicon structures on the oxide layer.

公开(公告)号：US12237372B2

公开(公告)日：2025-02-25

申请号：US18295246

申请日：2023-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Jia-Ni Yu ,  Chung-Wei Hsu ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Mao-Lin Huang

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

公开(公告)号：US12198986B2

公开(公告)日：2025-01-14

申请号：US18366562

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Sheng Yun ,  Chih-Hao Wang ,  Jui-Chien Huang ,  Kuo-Cheng Chiang ,  Chih-Chao Chou ,  Chun-Hsiung Lin ,  Pei-Hsun Wang

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/311 ,  H01L21/324 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.

公开(公告)号：US12166100B2

公开(公告)日：2024-12-10

申请号：US18447006

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu ,  Chih-Hao Wang

IPC: H01L29/51 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are separated and stacked up, and a thickness of each second semiconductor layer is less than a thickness of each first semiconductor layer; a first interfacial layer around each first semiconductor layer; a second interfacial layer around each second semiconductor layer; a first dipole gate dielectric layer around each first semiconductor layer and over the first interfacial layer; a second dipole gate dielectric layer around each second semiconductor layer and over the second interfacial layer; a first gate electrode around each first semiconductor layer and over the first dipole gate dielectric layer; and a second gate electrode around each second semiconductor layer and over the second dipole gate dielectric layer.

公开(公告)号：US20240363759A1

公开(公告)日：2024-10-31

申请号：US18768357

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78612 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0921 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device according to the present disclosure includes an active region including a channel region and a source/drain region adjacent the channel region, a vertical stack of channel members over the channel region, a gate structure over and around the vertical stack of channel members, a bottom dielectric feature over the source/drain region, a source/drain feature over the bottom dielectric feature, and a germanium layer disposed between the bottom dielectric feature and the source/drain region.

公开(公告)号：US12107131B2

公开(公告)日：2024-10-01

申请号：US18328520

申请日：2023-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes a first interconnect structure and multiple channel layers stacked over the first interconnect structure. A bottommost one of the multiple channel layers is thinner than rest of the multiple channel layers. The semiconductor device further includes a gate stack wrapping around each of the channel layers except a bottommost one of the channel layers; a source/drain feature adjoining the channel layers; a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature; and a dielectric feature under the bottommost one of the channel layers and directly contacting the first conductive via.