公开(公告)号：US20160062226A1

公开(公告)日：2016-03-03

申请号：US14471880

申请日：2014-08-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Yu LIN ,  Yi-Jie CHEN ,  Feng-Yuan CHIU ,  Ying-Chou CHENG ,  Kuei-Liang LU ,  Ya-Hui CHANG ,  Ru-Gun LIU ,  Tsai-Sheng GAU

IPC: G03F1/42 ,  G06F17/50 ,  G03F1/36

CPC classification number: G03F1/42 ,  G03F1/36 ,  G03F7/038 ,  G06F17/5072

Abstract: A photomask and method for fabricating an integrated circuit is provided. The photomask includes a plurality of main features, enclosed in at least one first region and at least one second region, wherein the first region comprises single the main feature and the second region comprises multiple the main features; and a plurality of assistant features disposed between the first region and the second region, or between the second regions. The photomask enhances the accuracy of the critical dimension and facilitate fabricating an integrated circuit.

Abstract translation: 提供一种用于制造集成电路的光掩模和方法。 光掩模包括封闭在至少一个第一区域和至少一个第二区域中的多个主要特征，其中第一区域包括单个主要特征，而第二区域包括多个主要特征; 以及设置在第一区域和第二区域之间或第二区域之间的多个辅助特征。 光掩模提高了临界尺寸的精度，并有助于制造集成电路。

公开(公告)号：US20240087896A1

公开(公告)日：2024-03-14

申请号：US18516719

申请日：2023-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Min HSIAO ,  Chien-Wen LAI ,  Ru-Gun LIU ,  Chih-Ming LAI ,  Shih-Ming CHANG ,  Yung-Sung YEN ,  Yu-Chen CHANG

IPC: H01L21/033 ,  H01L21/265 ,  H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/0338 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/26586 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31155

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

公开(公告)号：US20230152710A1

公开(公告)日：2023-05-18

申请号：US18153708

申请日：2023-01-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Ming CHANG ,  Chiu-Hsiang CHEN ,  Ru-Gun LIU

IPC: G03F7/20

CPC classification number: G03F7/70341 ,  G03F7/2041 ,  G03F7/2006 ,  G03F7/2004

Abstract: A method of operating a semiconductor apparatus includes generating an air flow that flows from a covering structure; causing a photomask to move over the covering structure such that particles attached to the photomask are blown away from the photomask by the air flow; and irradiating the photomask with light through a light transmission region of the covering structure.

公开(公告)号：US20220359203A1

公开(公告)日：2022-11-10

申请号：US17869707

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Min HSIAO ,  Chien-Wen LAI ,  Ru-Gun LIU ,  Chih-Ming LAI ,  Shih-Ming CHANG ,  Yung-Sung YEN ,  Yu-Chen CHANG

IPC: H01L21/033 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/265

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

公开(公告)号：US20210382399A1

公开(公告)日：2021-12-09

申请号：US17411571

申请日：2021-08-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Ming CHANG ,  Chiu-Hsiang CHEN ,  Ru-Gun LIU

IPC: G03F7/20

Abstract: A method of operating a semiconductor apparatus includes generating an electric field in peripheral areas of a first covering structure and a second covering structure; causing a photomask to move to a position between the first and second covering structures such that the photomask at least partially vertically overlaps the first and second covering structures and such that particles attached to the photomask are attracted to the first and second covering structures by the electric field; and irradiating the photomask with light through light transmission regions of the first and second covering structures.

公开(公告)号：US20210272808A1

公开(公告)日：2021-09-02

申请号：US16806206

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Min HSIAO ,  Chien-Wen LAI ,  Ru-Gun LIU ,  Chih-Ming LAI ,  Shih-Ming CHANG ,  Yung-Sung YEN ,  Yu-Chen CHANG

IPC: H01L21/033 ,  H01L21/265 ,  H01L21/311 ,  H01L21/3115

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

公开(公告)号：US20210242136A1

公开(公告)日：2021-08-05

申请号：US17239962

申请日：2021-04-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chiu-Hsiang CHEN ,  Shih-Chun HUANG ,  Yung-Sung YEN ,  Ru-Gun LIU

IPC: H01L23/544 ,  H01L27/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/308 ,  H01L21/027 ,  G06F30/392

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming an alignment mark in a material layer, wherein the alignment mark has a step sidewall in the material layer, and the step sidewall of the alignment mark has a floor surface portion; forming a feature material over the material layer; and performing a planarization process at least on the feature material, wherein the planarization process stops at a level higher than the floor surface portion of the step sidewall of the alignment mark.

公开(公告)号：US20210191254A1

公开(公告)日：2021-06-24

申请号：US17195469

申请日：2021-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Ting HUANG ,  Shih-Hsiang LO ,  Ru-Gun LIU

IPC: G03F1/36

Abstract: A method for mask data synthesis and mask making includes calibrating an optical proximity correction (OPC) model by adjusting a plurality of parameters including a first parameter and a second parameter, wherein the first parameter indicates a long-range effect caused by an electron-beam lithography tool for making a mask used to manufacture a structure, and the second parameter indicates a geometric feature of a structure or a manufacturing process to make the structure, generating a device layout, calculating a first grid pattern density map of the device layout, generating a long-range correction map, at least based on the calibrated OPC model and the first grid pattern density map of the device layout, and performing an OPC to generate a corrected mask layout, at least based on the generated long-range correction map and the calibrated OPC model.

公开(公告)号：US20210082903A1

公开(公告)日：2021-03-18

申请号：US17092100

申请日：2020-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Charles Chew-Yuen YOUNG ,  Chih-Liang CHEN ,  Chih-Ming LAI ,  Jiann-Tyng TZENG ,  Shun-Li CHEN ,  Kam-Tou SIO ,  Shih-Wei PENG ,  Chun-Kuang CHEN ,  Ru-Gun LIU

IPC: H01L27/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  G06F30/394

Abstract: A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

公开(公告)号：US20200335340A1

公开(公告)日：2020-10-22

申请号：US16921032

申请日：2020-07-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Chun HUANG ,  Chiu-Hsiang CHEN ,  Ya-Wen YEH ,  Yu-Tien SHEN ,  Po-Chin CHANG ,  Chien Wen LAI ,  Wei-Liang LIN ,  Ya Hui CHANG ,  Yung-Sung YEN ,  Li-Te LIN ,  Pinyen LIN ,  Ru-Gun LIU ,  Chin-Hsiang LIN

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265

Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.