公开(公告)号：US11869581B2

公开(公告)日：2024-01-09

申请号：US17749325

申请日：2022-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Pao ,  Shih-Hao Lin ,  Kian-Long Lim

IPC: G11C11/418 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/419

Abstract: Memory systems are provided. In an embodiment, a memory device includes a word line driver coupled to a plurality of word lines, a recycle multiplexer coupled to a plurality of bit lines and a plurality of bit line bars, a memory cell array, and a compensation word line driver. The memory cell array includes a first end adjacent the word line driver, a second end away from the word line driver, and a plurality of memory cells. The compensation word line driver is disposed adjacent the second end of the memory cell array and coupled to the plurality of word lines. The recycle multiplexer is configured to selectively couple one or more of the plurality of bit lines or one or more of the plurality of bit line bars to the compensation word line driver.

公开(公告)号：US20230369496A1

公开(公告)日：2023-11-16

申请号：US18359034

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen Su ,  Yu-Kuan Lin ,  Chih-Chuan Yang ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/76224 ,  H01L21/02579 ,  H01L21/02576 ,  H01L21/02532

Abstract: A semiconductor device includes a memory macro having a middle strap area between edges of the memory macro and memory bit areas on both sides of the middle strap area. The memory macro includes n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells. The n-type and the p-type wells extend lengthwise along a second direction and extend continuously through the middle strap area and the memory bit areas. The memory macro includes a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas. From a top view, the first dielectric layer extends along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area. From a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.

公开(公告)号：US11749340B2

公开(公告)日：2023-09-05

申请号：US17843241

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Shih-Hao Lin

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419 ,  H01L21/475 ,  H10B10/00

CPC classification number: G11C11/412 ,  G11C11/419 ,  H01L21/475 ,  H10B10/12

Abstract: Semiconductor devices and methods are provided. A semiconductor device of the present disclosure includes a bias source, a memory cell array including a first region adjacent to the bias source and a second region away from the bias source, and a conductive line electrically coupled to the bias source, a first memory cell in the first region and a second memory cell in the second region. The first memory cell is characterized by a first alpha ratio and the second memory cell is characterized by a second alpha ratio smaller than the first alpha ratio.

公开(公告)号：US11462282B2

公开(公告)日：2022-10-04

申请号：US16837227

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen Su ,  Kian-Long Lim ,  Wen-Chun Keng ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC: G11C17/18 ,  G11C7/18 ,  H01L27/112

Abstract: A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.

公开(公告)号：US20220310783A1

公开(公告)日：2022-09-29

申请号：US17213402

申请日：2021-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bwo-Ning Chen ,  Xusheng Wu ,  Pin-Ju Liang ,  Chang-Miao Liu ,  Shih-Hao Lin

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.

公开(公告)号：US20220301646A1

公开(公告)日：2022-09-22

申请号：US17833419

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen Su ,  Shih-Hao Lin ,  Jui-Lin Chen ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: G11C17/16 ,  H01L27/112 ,  H01L29/06 ,  H01L21/265

Abstract: The present disclosure provides semiconductor device and methods of forming the same. A semiconductor device according to the present disclosure includes a gate structure, a source/drain feature adjacent the gate structure, a dielectric layer disclosed over the gate structure and the source/drain feature, a gate contact disposed in the dielectric layer and over the gate structure, and a source/drain contact disposed in the dielectric layer and over the source/drain feature. The dielectric layer is doped with a dopant and the dopant includes germanium or tin.

公开(公告)号：US11450673B2

公开(公告)日：2022-09-20

申请号：US16945146

申请日：2020-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chia-Hao Pao ,  Yu-Kuan Lin ,  Lien Jung Hung ,  Ping-Wei Wang ,  Shih-Hao Lin

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L27/11 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

公开(公告)号：US20220285369A1

公开(公告)日：2022-09-08

申请号：US17750649

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Chuan Yang ,  Chia-Hao Pao ,  Jing-Yi Lin

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

公开(公告)号：US11367479B2

公开(公告)日：2022-06-21

申请号：US16942278

申请日：2020-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Shih-Hao Lin

IPC: G11C16/04 ,  G11C11/412 ,  H01L21/475 ,  H01L27/11 ,  G11C11/419

Abstract: Semiconductor devices and methods are provided. A semiconductor device of the present disclosure includes a bias source, a memory cell array including a first region adjacent to the bias source and a second region away from the bias source, and a conductive line electrically coupled to the bias source, a first memory cell in the first region and a second memory cell in the second region. The first memory cell is characterized by a first alpha ratio and the second memory cell is characterized by a second alpha ratio smaller than the first alpha ratio.

公开(公告)号：US20220181332A1

公开(公告)日：2022-06-09

申请号：US17682061

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Lin Chen ,  Chao-Yuan Chang ,  Ping-Wei Wang ,  Fu-Kai Yang ,  Ting Fang ,  I-Wen Wu ,  Shih-Hao Lin

IPC: H01L27/11 ,  H01L29/417 ,  H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L29/40

Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.