公开(公告)号：US11227889B2

公开(公告)日：2022-01-18

申请号：US16674216

申请日：2019-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Tzu-Jui Wang ,  Yen-Ting Chiang ,  Yu-Jen Wang ,  Yuichiro Yamashita

IPC: H01L31/00 ,  H01L27/146

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensing element disposed within a semiconductor substrate. One or more isolation structures are arranged within one or more trenches disposed along a first surface of the semiconductor substrate. The one or more isolation structures are separated from opposing sides of the image sensing element by non-zero distances. The one or more trenches are defined by sidewalls and a horizontally extending surface of the semiconductor substrate. A doped region is laterally arranged between the sidewalls of the semiconductor substrate defining the one or more trenches and is vertically arranged between the image sensing element and the first surface of the semiconductor substrate.

公开(公告)号：US20210151495A1

公开(公告)日：2021-05-20

申请号：US16684871

申请日：2019-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Yimin Huang

IPC: H01L27/146

Abstract: The problem of reducing noise in image sensing devices, especially NIR detectors, is solved by providing ground connections for the reflectors. The reflectors may be grounded through vias that couple the reflectors to grounded areas of the substrate. The grounded areas of the substrate may be P+ doped areas formed proximate the surface of the substrate. In particular, the P+ doped areas may be parts of photodiodes. Alternatively, the reflectors may be grounded through a metal interconnect structure formed over the front side of the substrate.

公开(公告)号：US09728570B2

公开(公告)日：2017-08-08

申请号：US14935819

申请日：2015-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Chih-Hui Huang ,  Shyh-Fann Ting ,  Shih Pei Chou ,  Sheng-Chan Li

IPC: H01L21/00 ,  H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14689

Abstract: The present disclosure relates to a BSI image sensor with improved DTI structures, and an associated method of formation. In some embodiments, the BSI image sensor comprises a plurality of image sensing elements disposed within a substrate corresponding to a plurality of pixel regions. A deep trench isolation (DTI) grid is disposed between adjacent image sensing elements and extending from an upper surface of the substrate to positions within the substrate. The DTI grid comprises air-gaps disposed under the upper surface of the substrate, the air-gaps having lower portions surrounded by a first dielectric layer and some upper portions sealed by a second dielectric layer.

公开(公告)号：US20160276394A1

公开(公告)日：2016-09-22

申请号：US14663899

申请日：2015-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Keng-Yu Chou ,  Chun-Hao Chuang ,  Chien-Hsien Tseng ,  Shyh-Fann Ting ,  Wei-Chieh Chiang ,  Yuichiro Yamashita

IPC: H01L27/146

CPC classification number: H01L27/14645 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685

Abstract: A semiconductor structure for back side illumination (BSI) pixel sensors is provided. Photodiodes are arranged within a semiconductor substrate. A metal grid overlies the semiconductor substrate and is made up of metal grid segments that surround outer perimeters of the photodiodes, respectively, such that first openings within the metal grid overlie the photodiodes, respectively. A low-n grid is made up of low-n grid segments that surround the respective outer perimeters of the photodiodes, respectively, such that second openings within the low-n grid overlie the photodiodes, respectively. Color filters are arranged in the first and second openings of the photodiodes and have a refractive index greater than a refractive index of the low-n grid. A substrate isolation grid extends into the semiconductor substrate and is made up of isolation grid segments that surround outer perimeters of the photodiodes, respectively. A method for manufacturing the BSI pixel sensors is also provided.

Abstract translation: 提供了用于背面照明（BSI）像素传感器的半导体结构。 光电二极管布置在半导体衬底内。 金属网格覆盖半导体衬底，并且由分别围绕光电二极管的外周的金属栅格段组成，使得金属栅格内的第一开口分别覆盖在光电二极管上。 低n栅格分别由围绕光电二极管的相应外周的低n栅格段组成，使得低n栅格内的第二开口分别覆盖光电二极管。 滤光器布置在光电二极管的第一和第二开口中并且具有大于低n栅格的折射率的折射率。 衬底隔离栅格延伸到半导体衬底中，并且由分别围绕光电二极管外周的隔离栅格段组成。 还提供了用于制造BSI像素传感器的方法。

公开(公告)号：US20220223635A1

公开(公告)日：2022-07-14

申请号：US17321909

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsing-Chih Lin ,  Feng-Chi Hung ,  Shyh-Fann Ting

IPC: H01L27/146

Abstract: A semiconductor device includes a substrate having a front side and a back side opposite to each other. A plurality of photodetectors is disposed in the substrate within a pixel region. An isolation structure is disposed within the pixel region and between the photodetectors. The isolation structure includes a back side isolation structure extending from the back side of the substrate to a position in the substrate. A conductive plug structure is disposed in the substrate within a periphery region. A conductive cap is disposed on the back side of the substrate and extends from the pixel region to the periphery region and electrically connects the back side isolation structure to the conductive plug structure. A conductive contact lands on the conductive plug structure, and is electrically connected to the back side isolation structure through the conductive plug structure and the conductive cap.

公开(公告)号：US11069733B2

公开(公告)日：2021-07-20

申请号：US16815371

申请日：2020-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Shyh-Fann Ting ,  Yen-Ting Chiang ,  Yeur-Luen Tu ,  Min-Ying Tsai

IPC: H01L27/146

Abstract: In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures.

公开(公告)号：US20210183921A1

公开(公告)日：2021-06-17

申请号：US17187955

申请日：2021-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Shyh-Fann Ting ,  Yen-Ting Chiang ,  Yeur-Luen Tu ,  Min-Ying Tsai

IPC: H01L27/146

Abstract: In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures.

公开(公告)号：US10833119B2

公开(公告)日：2020-11-10

申请号：US15149561

申请日：2016-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chun Hsu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Jeng-Shyan Lin ,  Shyh-Fann Ting

IPC: H01L27/146 ,  H01L23/00

Abstract: The present disclosure relates to an integrated circuit having a bond pad with a relatively flat surface topography that mitigates damage to underlying layers. In some embodiments, the integrated circuit has a plurality of metal interconnect layers within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has a recess with sidewalls connecting a horizontal surface of the passivation structure to an upper surface of the passivation structure. A bond pad is arranged within the recess and has a lower surface overlying the horizontal surface. One or more protrusions extend outward from the lower surface through openings in the passivation structure to contact one of the metal interconnect layers. Arranging the bond pad within the recess and over the passivation structure mitigates stress to underlying layers during bonding without negatively impacting an efficiency of an image sensing element within the substrate.

公开(公告)号：US10658410B2

公开(公告)日：2020-05-19

申请号：US16113066

申请日：2018-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Shyh-Fann Ting ,  Yen-Ting Chiang ,  Yeur-Luen Tu ,  Min-Ying Tsai

IPC: H01L27/146 ,  H04N5/365 ,  H04N5/378

Abstract: In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures.

公开(公告)号：US20190214414A1

公开(公告)日：2019-07-11

申请号：US16352108

申请日：2019-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Tzu-Jui Wang ,  Yen-Ting Chiang ,  Yu-Jen Wang ,  Yuichiro Yamashita

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

Abstract: The present disclosure, in some embodiments, relates to a method of forming an image sensor. The method includes implanting a dopant into a substrate to form a doped region and implanting one or more additional dopants into the substrate to form an image sensing element between the doped region and a front-side of the substrate. The doped region directly contacts a boundary of the image sensing element that is furthest from the front-side of the substrate. The method further includes etching the substrate to form one or more trenches extending into a back-side of the substrate. The back-side of the substrate opposes the front-side of the substrate. The method further includes filling the one or more trenches with one or more dielectric materials to form isolation structures.