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公开(公告)号：US20190123274A1
公开(公告)日：2019-04-25
申请号：US16217134
申请日：2018-12-12
Inventor： Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang , Kuo-Chi Tu , Wen-Ting Chu , Yu-Wen Liao
IPC: H01L45/00
CPC classification number: H01L45/1253 , H01L45/04 , H01L45/122 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1666 , H01L45/1675
Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
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公开(公告)号：US20190051702A1
公开(公告)日：2019-02-14
申请号：US16160675
申请日：2018-10-15
Inventor： Chin-Chieh Yang , Hsia-Wei Chen , Chih-Yang Chang , Kuo-Chi Tu , Wen-Ting Chu , Yu-Wen Liao
IPC: H01L27/24 , H01L29/66 , H01L45/00 , H01L21/265 , H01L21/266 , H01L29/78 , H01L29/08
CPC classification number: H01L27/2436 , H01L21/26513 , H01L21/266 , H01L29/0847 , H01L29/66659 , H01L29/7835 , H01L45/04 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1625
Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain of the FET has a higher doping concentration than the source of the FET. The resistive memory element is coupled with the drain via a portion of an interconnect structure.
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公开(公告)号：US09780145B2
公开(公告)日：2017-10-03
申请号：US15167905
申请日：2016-05-27
Inventor： Chih-Yang Chang , Wen-Ting Chu , Kuo-Chi Tu , Yu-Wen Liao , Hsia-Wei Chen , Chin-Chieh Yang
IPC: H01L29/76 , H01L29/788 , H01L27/24 , H01L45/00
CPC classification number: H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1675
Abstract: A resistive random access memory (RRAM) cell comprises a transistor having a gate and a source/drain region, a bottom electrode coplanar with the gate, a resistive material layer over the bottom electrode, a top electrode over the resistive material layer, and a conductive material electrically connecting the bottom electrode to the source/drain region.
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公开(公告)号：US09673391B2
公开(公告)日：2017-06-06
申请号：US15094371
申请日：2016-04-08
Inventor： Kuo-Chi Tu , Chih-Yang Chang , Hsia-Wei Chen , Yu-Wen Liao , Chin-Chieh Yang , Wen-Ting Chu
IPC: H01L45/00
CPC classification number: H01L45/146 , H01L45/08 , H01L45/1253 , H01L45/1616 , H01L45/1675
Abstract: A method includes forming a protection material over a conductive structure, an opening over the structure is partially filled with a first electrode material to form a first electrode; a resistance variable layer and a second electrode material are also formed in the opening. The second electrode material and the resistance variable layer are patterned to form a memory element. The method includes forming an interlayer dielectric over the memory element and the periphery region of the substrate and disposing contacts in the interlayer dielectric.
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公开(公告)号：US09466794B2
公开(公告)日：2016-10-11
申请号：US14987621
申请日：2016-01-04
Inventor： Chin-Chieh Yang , Wen-Ting Chu , Yu-Wen Liao , Chih-Yang Chang , Hsia-Wei Chen , Kuo-Chi Tu , Ching-Pei Hsieh
IPC: H01L21/20 , H01L21/311 , H01L45/00 , H01L27/24
CPC classification number: H01L45/1608 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/1273 , H01L45/146 , H01L45/16 , H01L45/1675
Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a non-planar portion, a resistive material layer conformally covering the non-planar portion of the bottom electrode; and, a top electrode on the resistive material layer. The via portion of the bottom electrode is embedded in a first RRAM stop layer. The non-planar portion of the bottom electrode has an apex and is centered above the via portion.
Abstract translation: 本公开提供了一种电阻随机存取存储器（RRAM）单元及其制造方法。 RRAM单元包括晶体管和RRAM结构。 RRAM结构包括具有通孔部分和非平面部分的底部电极，保形地覆盖底部电极的非平面部分的电阻材料层; 以及电阻材料层上的顶部电极。 底部电极的通孔部分嵌入第一RRAM停止层。 底部电极的非平面部分具有顶点并且在通孔部分上方居中。
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Patent Agency Ranking
公开(公告)号：US09349953B2
公开(公告)日：2016-05-24
申请号：US13896023
申请日：2013-05-16
Inventor： Kuo-Chi Tu , Chih-Yang Chang , Hsia-Wei Chen , Yu-Wen Liao , Chin-Chieh Yang , Wen-Chun You , Sheng-Hung Shih , Wen-Ting Chu
IPC: H01L45/00
CPC classification number: H01L45/146 , H01L45/08 , H01L45/1253 , H01L45/1616 , H01L45/1675
Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.
Abstract translation: 半导体结构包括存储区。 存储器结构设置在存储器区域上。 存储器结构包括第一电极，电阻变化层，保护间隔物和第二电极。 第一电极具有顶表面和存储区上的第一外侧壁表面。 电阻变化层具有第一部分和第二部分。 第一部分设置在第一电极的顶表面上，第二部分从第一部分向上延伸。 保护间隔物设置在第一电极的顶表面的一部分上并且围绕电阻变化层的第二部分。 保护间隔件可配置为保护电阻变化层中的至少一个导电路径。 保护间隔件具有基本上与第一电极的第一外侧壁表面对齐的第二外侧壁表面。
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公开(公告)号：US20160118584A1
公开(公告)日：2016-04-28
申请号：US14987621
申请日：2016-01-04
Inventor： Chin-Chieh Yang , Wen-Ting Chu , Yu-Wen Liao , Chih-Yang Chang , Hsia-Wei Chen , Kuo-Chi Tu , Ching-Pei Hsieh
CPC classification number: H01L45/1608 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/1273 , H01L45/146 , H01L45/16 , H01L45/1675
Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a non-planar portion, a resistive material layer conformally covering the non-planar portion of the bottom electrode; and, a top electrode on the resistive material layer. The via portion of the bottom electrode is embedded in a first RRAM stop layer. The non-planar portion of the bottom electrode has an apex and is centered above the via portion.
Abstract translation: 本公开提供了一种电阻随机存取存储器（RRAM）单元及其制造方法。 RRAM单元包括晶体管和RRAM结构。 RRAM结构包括具有通孔部分和非平面部分的底部电极，保形地覆盖底部电极的非平面部分的电阻材料层; 以及电阻材料层上的顶部电极。 底部电极的通孔部分嵌入第一RRAM停止层。 底部电极的非平面部分具有顶点并且在通孔部分上方居中。
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公开(公告)号：US09130162B2
公开(公告)日：2015-09-08
申请号：US13722466
申请日：2012-12-20
Inventor： Kuo-Chi Tu , Chih-Yang Chang , Hsia-Wei Chen , Yu-Wen Liao , Chin-Chieh Yang , Wen-Ting Chu
CPC classification number: H01L45/1253 , H01L27/2436 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/124 , H01L45/14 , H01L45/146 , H01L45/1608 , H01L45/1675
Abstract: A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer.
Abstract translation: 半导体结构包括电阻变化存储器结构。 半导体结构还包括电介质层。 电阻可变存储器结构在电介质层之上。 电阻可变存储器结构包括设置在电介质层上的第一电极。 第一电极具有侧壁表面。 电阻变化层具有设置在第一电极的侧壁表面上的第一部分和从第一部分延伸离开第一电极的第二部分。 第二电极在电阻变化层之上。
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49.发明申请ONE TRANSISTOR AND ONE RESISTIVE (1T1R) RANDOM ACCESS MEMORY (RAM) STRUCTURE WITH DUAL SPACERS 审中-公开一个晶体管和一个电阻（1T1R）随机访问存储器（RAM）结构与双重间隔公开(公告)号：US20150147864A1
公开(公告)日：2015-05-28
申请号：US14607955
申请日：2015-01-28
Inventor： Yu-Wen Liao , Wen-Ting Chung-Shi , Kuo-Chi Tu , Chih-Yang Chang , Chin-Chieh Yang , Hsia-Wei Chen , Ching-Pei Hsieh
CPC classification number: H01L45/1608 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1675
Abstract: The present disclosure provides methods of making resistive random access memory (RRAM) cells. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode, a first spacer surrounding the capping layer and a top electrode, a second spacer surround the top portion of the bottom electrode and the first spacer, and the top electrode. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.
Abstract translation: 本公开提供了制造电阻随机存取存储器（RRAM）单元的方法。 RRAM单元包括晶体管和RRAM结构。 RRAM结构包括具有通孔部分和顶部部分的底部电极，底部电极上的电阻材料层具有与底部电极的顶部部分的宽度相同的宽度; 覆盖在所述底部电极上的覆盖层，围绕所述覆盖层的第一间隔物和顶部电极，围绕所述底部电极和所述第一间隔物的顶部以及所述顶部电极的第二间隔物。 RRAM单元还包括将RRAM结构的顶部电极连接到金属层的导电材料。
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公开(公告)号：US08952347B2
公开(公告)日：2015-02-10
申请号：US13791659
申请日：2013-03-08
Inventor： Chih-Yang Chang , Wen-Ting Chu , Kuo-Chi Tu , Hsia-Wei Chen , Yu-Wen Liao , Chin-Chieh Yang
CPC classification number: H01L45/1666 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1675 , Y10S438/90
Abstract: A method for forming a resistive memory cell within a memory array includes forming a patterned stopping layer on a first metal layer formed on a substrate and forming a bottom electrode into features of the patterned stopping layer. The method further includes forming a resistive memory layer. The resistive memory layer includes a metal oxide layer and a top electrode layer. The method further includes patterning the resistive memory layer so that the top electrode layer acts as a bit line within the memory array and a top electrode of the resistive memory cell.
Abstract translation: 用于在存储器阵列内形成电阻存储单元的方法包括在形成在衬底上的第一金属层上形成图案化的阻挡层，并形成底部电极作为图案化阻挡层的特征。 该方法还包括形成电阻存储层。 电阻性存储层包括金属氧化物层和顶部电极层。 该方法还包括图案化电阻性存储层，使得顶部电极层用作存储器阵列内的位线和电阻存储器单元的顶部电极。
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