公开(公告)号：US11307987B2

公开(公告)日：2022-04-19

申请号：US16882305

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Naveen Bhoria ,  Peter Michael Hippleheuser

IPC: G06F12/0811 ,  G06F12/0808 ,  G06F12/0895 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0815 ,  G06F12/128 ,  G06F12/0817 ,  G06F9/30 ,  G06F11/30 ,  G06F13/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54

Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem by a transaction bus and a tag update bus. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives a message from the L1 controller over the tag update bus, including a valid signal, an address, and a coherence state. In response to the valid signal being asserted, the L2 controller identifies an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the message and updates a coherence state of the identified entry to be the coherence state of the message.

公开(公告)号：US11243883B2

公开(公告)日：2022-02-08

申请号：US16882257

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Timothy David Anderson ,  Kai Chirca

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/084 ,  G06F9/30 ,  G06F11/30 ,  G06F12/0808 ,  G06F13/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F12/0895

Abstract: A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.

公开(公告)号：US11106584B2

公开(公告)日：2021-08-31

申请号：US16882216

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Naveen Bhoria

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/084 ,  G06F9/30 ,  G06F11/30 ,  G06F12/0808 ,  G06F13/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F12/0895

Abstract: A system includes a non-coherent component; a coherent, non-caching component; a coherent, caching component; and a level two (L2) cache subsystem coupled to the non-coherent component, the coherent, non-caching component, and the coherent, caching component. The L2 cache subsystem includes a L2 cache; a shadow level one (L1) main cache; a shadow L1 victim cache; and a L2 controller. The L2 controller is configured to receive and process a first transaction from the non-coherent component; receive and process a second transaction from the coherent, non-caching component; and receive and process a third transaction from the coherent, caching component.

公开(公告)号：US12197332B2

公开(公告)日：2025-01-14

申请号：US18584181

申请日：2024-02-22

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  Timothy Anderson ,  Kai Chirca ,  David Matthew Thompson

IPC: G06F12/00 ,  G06F1/14 ,  G06F9/38 ,  G06F9/54 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0888

Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

公开(公告)号：US12197331B2

公开(公告)日：2025-01-14

申请号：US18487196

申请日：2023-10-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Naveen Bhoria ,  Pete Michael Hippleheuser

IPC: G06F12/0811 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F11/30 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/16

Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem including a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller configured to receive a read request from the L1 controller as a single transaction. Read request includes a read address, a first indication of an address and a coherence state of a cache line A to be moved from the L1 main cache to the L1 victim cache to allocate space for data returned in response to the read request, and a second indication of an address and a coherence state of a cache line B to be removed from the L1 victim cache in response to the cache line A being moved to the L1 victim cache.

公开(公告)号：US20240345956A1

公开(公告)日：2024-10-17

申请号：US18754499

申请日：2024-06-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Naveen BHORIA ,  Peter Michael HIPPLEHEUSER

IPC: G06F12/0811 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F11/30 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/16

CPC classification number: G06F12/0811 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/3867 ,  G06F9/467 ,  G06F9/544 ,  G06F9/546 ,  G06F11/3037 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/1668 ,  G06F2212/1021 ,  G06F2212/608

Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem by a transaction bus and a tag update bus. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives a message from the L1 controller over the tag update bus, including a valid signal, an address, and a coherence state. In response to the valid signal being asserted, the L2 controller identifies an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the message and updates a coherence state of the identified entry to be the coherence state of the message.

公开(公告)号：US20240281329A1

公开(公告)日：2024-08-22

申请号：US18654109

申请日：2024-05-03

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  David Matthew Thompson ,  Daniel Brad Wu

IPC: G06F11/10 ,  G06F3/06 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/126 ,  H04W24/10 ,  H04W56/00 ,  H04W72/02 ,  H04W72/044 ,  H04W74/08 ,  H04W74/0833

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0685 ,  G06F9/3816 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/126 ,  H04W24/10 ,  H04W56/001 ,  H04W72/02 ,  H04W72/044 ,  H04W74/0841 ,  H04W74/0866 ,  G06F3/0604 ,  G06F2212/608

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, and a cache memory with a memory controller having a memory pipeline. The cache memory has cache lines of length L. The cache memory has a minimum write length that is less than a cache line length of the cache memory. The memory pipeline determines whether the data payload includes a first chunk and ECC syndrome that correspond to a partial write and are writable by a first cache write operation, and a second chunk and ECC syndrome that correspond to a full write operation that can be performed separately from the first cache write operation. The memory pipeline performs an RMW operation to store the first chunk and ECC syndrome in the cache memory, and performs the full write operation to store the second chunk and ECC syndrome in the cache memory.

公开(公告)号：US12056051B2

公开(公告)日：2024-08-06

申请号：US17723559

申请日：2022-04-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Naveen Bhoria ,  Peter Michael Hippleheuser

IPC: G06F12/0811 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F11/30 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/16

CPC classification number: G06F12/0811 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/3867 ,  G06F9/467 ,  G06F9/544 ,  G06F9/546 ,  G06F11/3037 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/1668 ,  G06F2212/1021 ,  G06F2212/608

Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem by a transaction bus and a tag update bus. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives a message from the L1 controller over the tag update bus, including a valid signal, an address, and a coherence state. In response to the valid signal being asserted, the L2 controller identifies an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the message and updates a coherence state of the identified entry to be the coherence state of the message.

公开(公告)号：US20240256464A1

公开(公告)日：2024-08-01

申请号：US18630098

申请日：2024-04-09

Applicant: Texas Instruments Incorporated

Inventor： Bipin Prasad Heremagalur Ramaprasad ,  David Matthew Thompson ,  Abhijeet Ashok Chachad ,  Hung Ong

IPC: G06F12/1045 ,  G06F15/78

CPC classification number: G06F12/1045 ,  G06F15/7807 ,  G06F2212/301 ,  G06F2212/50

Abstract: A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.

公开(公告)号：US20240168883A1

公开(公告)日：2024-05-23

申请号：US18425165

申请日：2024-01-29

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  David Matthew Thompson

IPC: G06F12/0842 ,  G06F1/14 ,  G06F9/38 ,  G06F9/54 ,  G06F12/0811 ,  G06F12/0888

CPC classification number: G06F12/0842 ,  G06F1/14 ,  G06F9/38 ,  G06F9/544 ,  G06F12/0811 ,  G06F12/0888 ,  G06F2212/1016

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory controller. The memory controller has a memory pipeline. The memory controller is coupled to control the cache memory and communicatively coupled to the processor core. The memory controller is configured to receive the memory write requests from the processor core; schedule the memory write requests on the memory pipeline; and contemporaneously with scheduling respective ones of the memory write requests on the memory pipeline, send to the processor core a write acknowledgment confirming that writing of a data payload of the respective memory write request to the cache memory has completed.