公开(公告)号：US06304122B1

公开(公告)日：2001-10-16

申请号：US09641425

申请日：2000-08-17

申请人： Roger P. Gregor ,  Steven F. Oakland ,  Toshiharu Saitoh ,  Sebastian T. Ventrone

发明人： Roger P. Gregor ,  Steven F. Oakland ,  Toshiharu Saitoh ,  Sebastian T. Ventrone

IPC分类号： H03K3289

CPC分类号： H03K3/0375 ,  H03K3/0372

摘要： This invention reduces power in flip flop apparatuses by providing flip flop apparatuses that have fewer clock trees than prior art flip flops yet still support some or all of the Level Sensitive Scan Design (LSSD) functionality. In preferred embodiments of the present invention, one clock tree is used instead of two to provide lower power, and less switching devices in clocks splitters are used, which also provides lower power. Additionally, a flushable single clock splitter is provided that allows one clock tree to be used up to the flushable single clock splitter and provides two clocks on the output of the flushable single clock splitter. This saves some power yet still allows for dual clock flip flop designs.

摘要翻译： 本发明通过提供具有比现有技术的触发器更少的时钟树的触发器装置来降低触发器装置的功率，但仍然支持一些或全部级别敏感扫描设计（LSSD）功能。 在本发明的优选实施例中，使用一个时钟树来代替两个时钟树来提供较低的功率，并且使用时钟分配器中的较少的开关器件，其也提供较低的功率。 另外，提供了一个可冲洗的单时钟分离器，其允许一个时钟树被使用到可冲洗的单时钟分离器，并且在可冲洗单时钟分离器的输出端上提供两个时钟。 这节省了一些功耗，但仍然允许双时钟触发器设计。

公开(公告)号：US06253299B1

公开(公告)日：2001-06-26

申请号：US09224793

申请日：1999-01-04

申请人： Jack R. Smith ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Jack R. Smith ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G06F1200

CPC分类号： G06F9/30112 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/30138 ,  G06F12/0875

摘要： A structure and method for processing data comprises a processing unit having a base cache, base registers having a base width and being operatively connected to the processing unit, and virtual cache registers having a virtual width and being located in the base cache and operatively connected to the processing unit, wherein a base processing precision of the processing system is determined by the base width of the base registers and a selectable enhanced processing precision is determined by the virtual width of the virtual cache registers, wherein the base registers store base instructions and data and the virtual cache registers store enhanced data, the virtual width being greater than the base width, and wherein the base cache includes tags identifying a portion of the base cache as the virtual registers, the virtual cache registers being accessible by the processing unit only for execution of enhanced instructions for providing the enhanced processing precision.

摘要翻译： 用于处理数据的结构和方法包括具有基本高速缓存，具有基本宽度并且可操作地连接到处理单元的基本寄存器的处理单元和具有虚拟宽度并位于基本高速缓存中并可操作地连接到 所述处理单元，其中所述处理系统的基本处理精度由所述基本寄存器的基本宽度确定，并且可选择的增强处理精度由所述虚拟高速缓存寄存器的虚拟宽度确定，其中所述基本寄存器存储基本指令和数据 并且所述虚拟高速缓存寄存器存储增强数据，所述虚拟宽度大于所述基本宽度，并且其中所述基本高速缓存包括标识所述基本高速缓存的一部分作为所述虚拟寄存器的标签，所述虚拟高速缓存寄存器仅由所述处理单元访问 执行增强的指令以提供增强的处理精度。

公开(公告)号：US6097243A

公开(公告)日：2000-08-01

申请号：US159861

申请日：1998-09-24

申请人： Claude L. Bertin ,  William Robert Patrick Tonti ,  Alvar Antonio Dean ,  Wilbur David Pricer ,  Patrick Edward Perry ,  Kenneth J. Goodnow ,  Sebastian T. Ventrone

发明人： Claude L. Bertin ,  William Robert Patrick Tonti ,  Alvar Antonio Dean ,  Wilbur David Pricer ,  Patrick Edward Perry ,  Kenneth J. Goodnow ,  Sebastian T. Ventrone

IPC分类号： G05F1/08 ,  G06F1/32 ,  G05F1/10

CPC分类号： G06F1/3203 ,  G06F1/3296 ,  Y02B60/1285

摘要： According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded node toggling in a circuit by utilizing either a pull-up or pull-down transistor to pull the input of the circuit to a state that minimizes power consumption during periods in which the circuit is inactive. By tying the circuit input high or low during inactivity, node toggling is reduced or eliminated in that circuit. In the preferred embodiment, the inputs to the circuit all pulled after a time of inactivity which is proportional to the leakage current of the leakiest transistor in the circuit. By timing the input pulling proportional to the leakage current, the power consumption is minimized without excessive power loss caused by the pulling itself.

摘要翻译： 根据优选实施例，提供了一种通过减少不需要的节点切换来降低功耗的装置和方法。 优选实施例通过利用上拉或下拉晶体管将电路中的输入引导到在电路不活动的时段期间最小化功耗的状态来减少电路中的不需要的节点切换。 通过在不活动状态下将电路输入高或低，在该电路中节点切换被减少或消除。 在优选实施例中，电路的输入在与电路中最漏电晶体管的漏电流成比例的不活动时间之后全部被拉。 通过定时输入拉动与泄漏电流成比例，最大限度地减少功耗，而不会由拉动本身引起的功率损耗过大。

公开(公告)号：US08612815B2

公开(公告)日：2013-12-17

申请号：US13327847

申请日：2011-12-16

申请人： Faraydon Pakbaz ,  Jack R. Smith ,  Sebastian T. Ventrone

发明人： Faraydon Pakbaz ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC分类号： G01R31/28

CPC分类号： G01R31/31813 ,  G01R31/3187

摘要： Disclosed are integrated circuits that incorporate an asynchronous circuit with a built-in self-test (BIST) architecture using a handshaking protocol for at-speed testing to detect stuck-at faults. Specifically, a test pattern generator applies test patterns to an asynchronous circuit and an analyzer analyzes the output test data. The handshaking protocol is achieved through the use of a single pulse generator, which applies a single pulse to the test pattern generator to force switching of the test pattern request signal and, thereby to control application of the test patterns to the asynchronous circuit and subsequent switching of the test pattern acknowledge signal. Generation of this single pulse can in turn be forced by the switching of the test pattern acknowledge signal.

摘要翻译： 公开了集成电路，其包括具有内置自检（BIST）架构的异步电路，其使用用于高速测试的握手协议来检测卡住的故障。 具体来说，测试模式发生器将测试模式应用于异步电路，分析仪分析输出测试数据。 握手协议通过使用单个脉冲发生器来实现，该单个脉冲发生器向测试模式发生器施加单个脉冲以强制测试模式请求信号的切换，从而控制测试模式对异步电路的应用和随后的切换 的测试模式确认信号。 可以通过切换测试模式确认信号来强制产生该单个脉冲。

公开(公告)号：US08424071B2

公开(公告)日：2013-04-16

申请号：US12621570

申请日：2009-11-19

申请人： Mariette Awad ,  Deanna C. Lim ,  Pascal A. Nsame ,  Daneyand J. Singley ,  Sebastian T. Ventrone

发明人： Mariette Awad ,  Deanna C. Lim ,  Pascal A. Nsame ,  Daneyand J. Singley ,  Sebastian T. Ventrone

IPC分类号： G06F7/04

CPC分类号： G06F21/55 ,  G06F21/31

摘要： In one embodiment, the invention is a method and apparatus for secure and reliable computing. One embodiment of an end-to-end security system for protecting a computing system includes a processor interface coupled to at least one of an application processor and an accelerator of the computing system, for receiving requests from the at least one of the application processor and the accelerator, a security processor integrating at least one embedded storage unit and connected to the processor interface with a tightly coupled memory unit for performing at least one of: authenticating, managing, monitoring, and processing the requests, and a data interface for communicating with a display, a network, and at least one embedded storage unit for securely holding at least one of data and programs used by the at least one of the application processor and the accelerator.

公开(公告)号：US08122273B2

公开(公告)日：2012-02-21

申请号：US11870575

申请日：2007-10-11

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith Williams ,  Charles S. Woodruff

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith Williams ,  Charles S. Woodruff

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/26

摘要： A method and structure to optimize computational efficiency in a low-power environment. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a component to determine an optimal point for maximizing computational efficiency in a low-power environment, and a component to selectively control operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point. The design structure further includes at least one of a component for controlling a frequency of a clock signal transmitted to the at least one processing unit in accordance with the determined optimal point, and a component for determining a present power available.

摘要翻译： 一种在低功耗环境下优化计算效率的方法和结构。 设计结构体现在在设计过程中使用的机器可读介质中。 该设计结构包括确定用于在低功率环境中最大化计算效率的最佳点的组件，以及根据所确定的最佳点选择性地控制多个处理单元的至少一个处理单元的操作的组件。 该设计结构还包括用于根据确定的最佳点来控制发送到至少一个处理单元的时钟信号的频率的组件和用于确定当前可用功率的组件中的至少一个。

公开(公告)号：US07903493B2

公开(公告)日：2011-03-08

申请号：US12109379

申请日：2008-04-25

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Nitin Sharma ,  Sebastian T. Ventrone ,  Charles S. Woodruff

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Nitin Sharma ,  Sebastian T. Ventrone ,  Charles S. Woodruff

IPC分类号： G11C5/14

CPC分类号： G11C5/143

摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a threshold register having a counter, a count register, and a non-volatile storage for storing a state when a value of the count register equals or exceeds a value of the threshold register. Also provided is a method of predicting and/or estimating a power cycle duration in order to save a state in non-volatile memory and a circuit. The method includes setting a threshold value; determining that the threshold value has been equaled or exceeded; and saving the state in the non-volatile memory at a first checkpoint based on the threshold value being equaled or exceeded.

摘要翻译： 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括具有计数器，计数寄存器和非易失性存储器的阈值寄存器，用于当计数寄存器的值等于或超过阈值寄存器的值时存储状态。 还提供了一种预测和/或估计功率周期持续时间以便将状态保存在非易失性存储器和电路中的方法。 该方法包括设置阈值; 确定阈值已经相等或超过; 并且基于所述阈值相等或超过，在第一检查点处将所述状态保存在所述非易失性存储器中。

公开(公告)号：US07898286B2

公开(公告)日：2011-03-01

申请号：US12369066

申请日：2009-02-11

申请人： Igor Arsovski ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Todd E. Leonard ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

发明人： Igor Arsovski ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Todd E. Leonard ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

IPC分类号： H03K19/00

CPC分类号： G01R31/31725

摘要： Cross-die connection structure and method for a die or chip includes buffer elements having a buffer driver and bypass, and control lines coupled to the buffer elements in order to select one of the buffer driver and bypass for each respective buffer element. A logic network is arranged with the buffer elements to form functional paths, a test unit is structured and arranged to test the functional paths and to be coupled to the control lines, and a configuration storage register to set the selected one of the buffer driver and bypass for each passing functional path.

摘要翻译： 用于管芯或芯片的跨管芯连接结构和方法包括具有缓冲器驱动器和旁路的缓冲器元件以及耦合到缓冲器元件的控制线，以便为每个相应的缓冲元件选择缓冲器驱动器和旁路中的一个。 逻辑网络被布置成具有缓冲元件以形成功能路径，测试单元被构造和布置以测试功能路径并耦合到控制线，以及配置存储寄存器，用于设置所选缓冲器驱动器和 绕过每个通过的功能路径。

公开(公告)号：US07872692B2

公开(公告)日：2011-01-18

申请号：US12056795

申请日：2008-03-27

申请人： Ahmed Y. Ginawi ,  Casey J. Grant ,  Christopher Ro ,  Sebastian T. Ventrone

发明人： Ahmed Y. Ginawi ,  Casey J. Grant ,  Christopher Ro ,  Sebastian T. Ventrone

IPC分类号： H04N5/50 ,  H04N5/44

CPC分类号： H04N7/163 ,  H04N21/4383 ,  H04N21/4394 ,  H04N21/44008 ,  H04N21/472 ,  H04N21/812

摘要： A design structure for systems for switching a displayed signal for a display between a plurality of signals are disclosed. In one embodiment, the design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and includes: a system for switching a displayed signal for a display between a plurality of signals, the system including: a microcontroller; a chooser for setting a primary signal from a plurality of program-variable signals; a monitor tuner coupled to the microcontroller for tuning the primary signal during switching of the displayed signal from the primary signal to a secondary signal; a detector coupled to the monitor tuner and the microcontroller for detecting a predetermined condition in the primary signal; and a selector coupled to the microcontroller for switching the displayed signal from the secondary signal to the primary signal upon occurrence of the predetermined condition.

摘要翻译： 公开了用于在多个信号之间切换用于显示的显示信号的系统的设计结构。 在一个实施例中，设计结构体现在用于设计，制造或测试集成电路的机器可读介质中，并且包括：用于在多个信号之间切换用于显示的显示信号的系统，所述系统包括：微控制器 ; 用于从多个可编程信号设置主信号的选择器; 耦合到微控制器的监视器调谐器，用于在将所显示的信号从主信号切换到辅助信号期间调谐主信号; 耦合到所述监视器调谐器和所述微控制器的检测器，用于检测所述主信号中的预定条件; 以及耦合到微控制器的选择器，用于在发生预定条件时将显示的信号从次级信号切换到主信号。

公开(公告)号：US20100333058A1

公开(公告)日：2010-12-30

申请号：US12875517

申请日：2010-09-03

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

IPC分类号： G06F17/50

CPC分类号： G01R31/31718 ,  G11C17/14 ,  G11C29/88 ,  H03K19/17764 ,  H03K19/17796

摘要： A method for increasing the manufacturing yield of field programmable gate arrays (FPGAs) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized.

摘要翻译： 一种提高现场可编程门阵列（FPGA）或其他可编程逻辑器件（PLD）的制造成品率的方法。 FPGA或其他PLD形成在几个部分中，每个部分都有自己的电源总线和输入/输出连接。 测试FPGA或其他PLD的每个部分，以识别FPGA或其他PLD中的缺陷。 FPGA或其他PLD根据该部分是否具有可接受的缺陷数量进行排序。 为FPGA或其他PLD芯片或部件分配的唯一编号将其识别为部分良好。 用于执行和配置FPGA或其他PLD的软件可以使用唯一编号仅对FPGA或其他PLD的已识别功能部分进行编程。 结果是产量增加，部分好的FPGA或其他PLD仍然可以被利用。