公开(公告)号：US11864468B2

公开(公告)日：2024-01-02

申请号：US17348776

申请日：2021-06-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Si-Han Tsai ,  Dong-Ming Wu ,  Chen-Yi Weng ,  Ching-Hua Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Che-Wei Chang ,  Po-Kai Hsu ,  Jing-Yin Jhang

IPC: G11C16/04 ,  H10N50/10 ,  H01F10/32 ,  G11C11/16 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  G11C11/161 ,  H01F10/3254 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

公开(公告)号：US11812669B2

公开(公告)日：2023-11-07

申请号：US17835986

申请日：2022-06-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  Jing-Yin Jhang ,  I-Ming Tseng ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Kun-Chen Ho ,  Yi-Syun Chou ,  Chang-Min Li ,  Yi-Wei Tseng ,  Yu-Tsung Lai ,  Jun Xie

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.

公开(公告)号：US11778920B2

公开(公告)日：2023-10-03

申请号：US17738001

申请日：2022-05-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Hung-Yueh Chen ,  Yu-Ping Wang

IPC: H10N50/01 ,  H10N50/80 ,  H10B61/00 ,  H10N50/85

CPC classification number: H10N50/01 ,  H10N50/80 ,  H10B61/00 ,  H10N50/85

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to and directly contacting the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is a single layer structure made of dielectric material and an edge of the cap layer contacts the first IMD layer directly.

公开(公告)号：US20230309414A1

公开(公告)日：2023-09-28

申请号：US18202275

申请日：2023-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Si-Han Tsai ,  Che-Wei Chang ,  Jing-Yin Jhang

IPC: H10B61/00 ,  H10N50/80

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

公开(公告)号：US11715499B2

公开(公告)日：2023-08-01

申请号：US17224153

申请日：2021-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kai Hsu ,  Hung-Yueh Chen ,  Kun-I Chou ,  Jing-Yin Jhang ,  Hui-Lin Wang ,  Yu-Ping Wang

IPC: G11C5/06 ,  H10B61/00 ,  H10B63/00

CPC classification number: G11C5/063 ,  H10B61/22 ,  H10B63/80

Abstract: A MRAM structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with storage units on corresponding active areas, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.

公开(公告)号：US20230232638A1

公开(公告)日：2023-07-20

申请号：US17673760

申请日：2022-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ju-Chun Fan ,  Ching-Hua Hsu ,  Chun-Hao Wang ,  Yi-Yu Lin ,  Dong-Ming Wu ,  Po-Kai Hsu

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C5/02 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/226 ,  H01L43/02 ,  H01L43/08 ,  G11C5/02 ,  H01L23/5226 ,  H01L23/5283

Abstract: Abstract of Disclosure A memory array includes at least one strap region, at least two sub-arrays, a plurality of staggered, dummy magnetic storage elements, and a plurality of bit line structures. The strap region includes a plurality of source line straps and a plurality of word line straps. The two sub-arrays include a plurality of staggered, active magnetic storage elements. The two sub -arrays are separated by the strap region. The staggered, dummy magnetic storage elements are disposed within the strap region. The bit line structures are disposed in the two sub-arrays, and each of the bit line structures is disposed above and directly connected with at least one of the staggered, active magnetic storage elements.

公开(公告)号：US20230110380A1

公开(公告)日：2023-04-13

申请号：US18079890

申请日：2022-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang

IPC: H10N50/80 ,  H10N50/01 ,  H10B61/00

Abstract: A semiconductor device includes a storage element on a substrate. The storage element has a tapered upper end structure. The tapered upper end structure includes a top electrode and a spacer surrounding the top electrode. A gap-fill dielectric layer is disposed around the spacer. A conductive cap layer covers the top electrode and the spacer. An inter-metal dielectric (IMD) layer is disposed on the conductive cap layer. A metal interconnection is disposed in the IMD layer and electrically connected to the top electrode through the conductive cap layer.

公开(公告)号：US20230050587A1

公开(公告)日：2023-02-16

申请号：US17980529

申请日：2022-11-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Yi Weng ,  Jing-Yin Jhang ,  Hui-Lin Wang ,  Chin-Yang Hsieh

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A spacer is formed on a sidewall of the MTJ structure and a sidewall of the connection structure. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.

公开(公告)号：US11545521B2

公开(公告)日：2023-01-03

申请号：US17157952

申请日：2021-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Chen ,  Hui-Lin Wang ,  Yu-Ru Yang ,  Chin-Fu Lin ,  Yi-Syun Chou ,  Chun-Yao Yang

IPC: H01L27/22 ,  H01L23/552 ,  H01L43/10 ,  H01F41/34 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

公开(公告)号：US20220376173A1

公开(公告)日：2022-11-24

申请号：US17343768

申请日：2021-06-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10

Abstract: A method of forming a semiconductor memory device is disclosed. A top electrode layer is formed on the MTJ stack layer. A patterned buffer layer is formed to cover only the logic circuit region. A hard mask layer is formed on the top electrode layer and the patterned buffer layer. A patterned resist layer is formed on the hard mask layer. A first etching process is performed to etch the hard mask layer and the top electrode layer not covered by the patterned resist layer in the memory region and the hard mask layer, the patterned buffer layer and the top electrode layer in the logic circuit region, thereby forming a top electrode on the MTJ stack layer in the memory region and a remaining top electrode layer covering only the logic circuit region on the MTJ stack layer.