公开(公告)号：US11004897B2

公开(公告)日：2021-05-11

申请号：US16531108

申请日：2019-08-04

申请人： UNITED MICROELECTRONICS CORP.

发明人： Kun-Ju Li ,  Tai-Cheng Hou ,  Hsin-Jung Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Chih-Yueh Li ,  Chun-Tsen Lu

IPC分类号： H01L29/82 ,  H01L27/22 ,  H01L43/12 ,  H01F41/34 ,  G11C11/16 ,  H01F10/32 ,  H01L43/02

摘要： A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.

公开(公告)号：US20210119110A1

公开(公告)日：2021-04-22

申请号：US16656304

申请日：2019-10-17

申请人： United Microelectronics Corp.

发明人： Da-Jun Lin ,  Bin-Siang Tsai ,  Ting-An Chien

IPC分类号： H01L43/02 ,  H01L43/10 ,  H01L43/12

摘要： A cell structure of magnetoresistive RAM includes a synthetic anti-ferromagnetic (SAF) layer to serve as a pinned layer; a barrier layer, disposed on the SAF layer; and a magnetic free layer, disposed on the barrier layer. The SAF layer includes: a first magnetic layer; a second magnetic layer; and a spacer layer of a first metal element sandwiched between the first magnetic layer and the second magnetic layer. The first metal element is phase separated from a second metal element of the first magnetic layer and the second magnetic layer interfacing with the spacer layer.

公开(公告)号：US10978339B2

公开(公告)日：2021-04-13

申请号：US16011615

申请日：2018-06-18

申请人： UNITED MICROELECTRONICS CORP.

发明人： Da-Jun Lin ,  Bin-Siang Tsai

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

摘要： A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first liner in the trench, wherein the first liner comprises Co—Ru alloy; forming a metal layer on the first liner; and planarizing the metal layer and the first liner to form a metal interconnection.

公开(公告)号：US20210050511A1

公开(公告)日：2021-02-18

申请号：US16563924

申请日：2019-09-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Da-Jun Lin ,  Tai-Cheng Hou ,  Bin-Siang Tsai ,  Ting-An Chien

IPC分类号： H01L43/12 ,  H01L43/02 ,  H01L27/22

摘要： A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a magnetic tunneling junction (MTJ) on the metal interconnection; forming a top electrode on the MTJ; and forming a trapping layer on the top electrode for trapping hydrogen. Preferably, the trapping layer includes a concentration gradient, in which a concentration of hydrogen decreases from a top surface of the top electrode toward the MTJ.

公开(公告)号：US10692758B1

公开(公告)日：2020-06-23

申请号：US16212362

申请日：2018-12-06

申请人： United Microelectronics Corp.

发明人： Da-Jun Lin ,  Bin-Siang Tsai ,  Chich-Neng Chang

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

摘要： A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. A porous dielectric layer is disposed over the substrate, sealing the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.

公开(公告)号：US10679893B2

公开(公告)日：2020-06-09

申请号：US16121605

申请日：2018-09-04

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yu-Cheng Lin ,  Chich-Neng Chang ,  Bin-Siang Tsai

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/522

摘要： An interconnection structure and method of forming the same are disclosed. A substrate is provided. A patterned layer is formed on the substrate and having at least a trench formed therein. A first dielectric layer is then formed on the patterned layer and sealing an air gap in the trench. Subsequently, a second dielectric layer is formed on the first dielectric layer and completely covering the patterned layer and the air gap. A curing process is then performed to the first dielectric layer and the second dielectric layer. A volume of the air gap is increased after the curing process.

公开(公告)号：US20180012793A1

公开(公告)日：2018-01-11

申请号：US15713724

申请日：2017-09-25

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chich-Neng Chang ,  Ya-Jyuan Hung ,  Bin-Siang Tsai

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/535

CPC分类号： H01L21/7682 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76895 ,  H01L23/5222 ,  H01L23/53295 ,  H01L23/535 ,  H01L2221/1063

摘要： A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer; forming an opening in the dielectric layer, wherein the dielectric layer comprises a damaged layer adjacent to the opening; forming a dielectric protective layer in the opening; forming a metal layer in the opening; removing the damaged layer and the dielectric protective layer to form a void, wherein the void exposes a top surface of the substrate; and forming a cap layer on and covering the dielectric layer, the void, and the metal layer.

公开(公告)号：US09530696B1

公开(公告)日：2016-12-27

申请号：US14921514

申请日：2015-10-23

申请人： United Microelectronics Corp.

发明人： Wei-Hsin Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Wei-Lun Hsu ,  Shang-Yi Yang ,  Pi-Hsuan Lai

IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/311 ,  H01L21/3105

CPC分类号： H01L21/823431 ,  H01L21/823425 ,  H01L21/823437 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device is provided. A plurality of sacrificial gates and a plurality of sacrificial gate dielectric layers thereunder are formed on a substrate. An interlayer dielectric layer is filled between the sacrificial gates. A protective layer is formed on the interlayer dielectric layer. The sacrificial gates and the sacrificial gate dielectric layers are removed to form an opening, wherein the interlayer dielectric layer is protected by the protective layer from recessing. A stacked gate structure is formed in the opening, wherein the protective layer is removed.

摘要翻译： 提供一种制造半导体器件的方法。 在基板上形成有多个牺牲栅极和其下的多个牺牲栅介质层。 在牺牲栅极之间填充层间电介质层。 在层间电介质层上形成保护层。 去除牺牲栅极和牺牲栅极电介质层以形成开口，其中层间介电层被保护层保护而不被凹陷。 在开口中形成堆叠的栅极结构，其中保护层被去除。

公开(公告)号：US20240243057A1

公开(公告)日：2024-07-18

申请号：US18124591

申请日：2023-03-22

申请人： UNITED MICROELECTRONICS CORP.

发明人： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L27/08

CPC分类号： H01L23/5223 ,  H01L21/76805 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/11 ,  H01L27/0805 ,  H01L2224/05026 ,  H01L2224/116 ,  H01L2924/19041 ,  H01L2924/30105

摘要： An integrated circuit includes a substrate, an interconnection layer, an insulation layer, a metal bump structure, and a metal-insulator-metal capacitor. The interconnection layer is disposed above the substrate. The interconnection layer includes an interlayer dielectric layer and an interconnection structure disposed in the interlayer dielectric layer. The insulation layer is disposed on the interconnection layer, the metal bump structure is disposed on the insulation layer, and the metal-insulator-metal capacitor is disposed conformally on the metal bump structure and the insulation layer. A manufacturing method of the integrated circuit includes the following steps.
The interconnection layer is formed above the substrate. The insulation layer is formed on the interconnection layer, the metal bump structure is formed on the insulation layer, and the metal-insulator-metal capacitor is formed conformally on the metal bump structure and the insulation layer.

公开(公告)号：US20240081154A1

公开(公告)日：2024-03-07

申请号：US18504176

申请日：2023-11-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Da-Jun Lin ,  Chau-Chung Hou ,  Wei-Xin Gao

IPC分类号： H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC分类号： H10N50/01 ,  H10B61/00 ,  H10N50/80

摘要： A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.