公开(公告)号：US11665978B2

公开(公告)日：2023-05-30

申请号：US16930291

申请日：2020-07-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  Rai-Min Huang ,  I-Fan Chang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10N50/80

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first patterned mask on the first IMD layer, in which the first patterned mask includes a first slot extending along a first direction; forming a second patterned mask on the first patterned mask, in which the second patterned mask includes a second slot extending along a second direction and the first slot intersects the second slot to form a third slot; and forming a first metal interconnection in the third slot.

公开(公告)号：US20210305316A1

公开(公告)日：2021-09-30

申请号：US16857152

申请日：2020-04-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  I-Fan Chang ,  Rai-Min Huang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L23/528 ,  H01L23/522 ,  G11C11/16 ,  H01F41/34 ,  H01F10/32

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, forming a magnetic tunneling junction (MTJ) on the MRAM region, forming a metal interconnection on the MTJ, forming a dielectric layer on the metal interconnection, patterning the dielectric layer to form openings, and forming the blocking layer on the patterned dielectric layer and the metal interconnection and into the openings.

公开(公告)号：US20210135092A1

公开(公告)日：2021-05-06

申请号：US16698924

申请日：2019-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Hung-Yueh Chen ,  Yu-Ping Wang ,  Jia-Rong Wu ,  Rai-Min Huang ,  Ya-Huei Tsai ,  I-Fan Chang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate and a dummy MTJ between the first MTJ and the second MTJ, in which a bottom surface of the dummy MTJ is not connected to any metal. Preferably, the semiconductor device further includes a first metal interconnection under the first MTJ, a second metal interconnection under the second MTJ, and a first inter-metal dielectric (IMD) layer around the first metal interconnection and the second metal interconnection and directly under the dummy MTJ.

公开(公告)号：US10944048B2

公开(公告)日：2021-03-09

申请号：US16554531

申请日：2019-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Huei Tsai ,  Rai-Min Huang

IPC: H01L43/08 ,  H01L43/02 ,  H01L27/22

Abstract: A semiconductor device includes a substrate, an array of magnetic tunnel junctions (MTJs), an array of first dummy MTJs, and an array of second dummy MTJs. The substrate includes an array region defined thereon, and the array region includes at least an outermost corner. The array of MTJs is disposed in the array region. The array of the first dummy MTJs is disposed along the outermost corner of the array region. The array of the second dummy MTJs is disposed around the array region and the array of first dummy MTJs.

公开(公告)号：US10930704B2

公开(公告)日：2021-02-23

申请号：US16812354

申请日：2020-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rai-Min Huang ,  Hung-Yueh Chen ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H01L27/22 ,  H01L23/532 ,  H01L43/02 ,  H01L23/522 ,  H01L23/528 ,  G11C11/16

Abstract: A magnetic memory cell includes a substrate, a transistor, a first dielectric layer disposed on the substrate, a landing pad in the first dielectric layer, a second dielectric layer covering the first dielectric layer and the landing pad, a memory stack in the second dielectric layer, and a source line in the first dielectric layer. The first dielectric layer covers the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region of the transistor. The memory stack has a bottom electrode connected to the landing pad and a top electrode electrically connected to a bit line. The source line is situated in a second horizontal plane and is connected to a source region of the transistor. The second horizontal plane and the first horizontal plane are not coplanar.

公开(公告)号：US09859147B2

公开(公告)日：2018-01-02

申请号：US15336811

申请日：2016-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tong-Jyun Huang ,  Rai-Min Huang ,  I-Ming Tseng ,  Kuan-Hsien Li ,  Chen-Ming Huang

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/02 ,  H01L27/088 ,  H01L21/3065

CPC classification number: H01L21/76224 ,  H01L21/02271 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653

Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.

公开(公告)号：US20160293726A1

公开(公告)日：2016-10-06

申请号：US14710602

申请日：2015-05-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rai-Min Huang ,  I-Ming Tseng ,  Tong-Jyun Huang ,  Kuan-Hsien Li

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/027 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/66545 ,  H01L21/3086 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/6656 ,  H01L29/785

Abstract: A patterned structure of a semiconductor device includes a substrate, a first feature and a second feature. The first feature and the second feature are disposed on the substrate, and either of which includes a vertical segment and a horizontal segment. There is a distance between the vertical segment of the first feature and the vertical segment of the second feature, and the distance is less than the minimum exposure limits of an exposure apparatus.

Abstract translation: 半导体器件的图案化结构包括衬底，第一特征和第二特征。 第一特征和第二特征设置在基板上，并且其中之一包括垂直段和水平段。 在第一特征的垂直段和第二特征的垂直段之间存在距离，并且该距离小于曝光设备的最小曝光极限。

公开(公告)号：US20150295090A1

公开(公告)日：2015-10-15

申请号：US14749648

申请日：2015-06-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hua Tsai ,  Rai-Min Huang ,  Sheng-Huei Dai ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/7853 ,  H01L21/02647 ,  H01L21/2022 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785 ,  H01L2029/7858

Abstract: A Fin-FET and a method of forming the Fin-FET are provided. A substrate is provided, and then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.

Abstract translation: 提供Fin-FET和形成Fin-FET的方法。 提供基板，然后在其上形成掩模层。 在衬底和掩模层中形成第一沟槽。 在第一沟槽中形成半导体层。 接下来，去除掩模层，使得半导体层变成嵌入在衬底中并突出在衬底上的散热片结构。 最后，在鳍结构上形成栅极层。

公开(公告)号：US20140225197A1

公开(公告)日：2014-08-14

申请号：US14261441

申请日：2014-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rai-Min Huang ,  Sheng-Huei Dai ,  Chen-Hua Tsai ,  Duan Quan Liao ,  Yikun Chen ,  Xiao Zhong Zhu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.

Abstract translation: FINFET晶体管结构包括衬底，鳍结构，绝缘层和栅极结构。 翅片结构设置在基板上并直接连接到基板。 此外，翅片结构包括翅片导电层和瓶颈。 绝缘层覆盖基板，并且具有通过部分地围绕翅片结构的瓶颈而形成的突出侧，以及与基板直接接触的底侧，使得突出侧延伸到翅片结构的下方。 门结构部分地围绕翅片结构。

公开(公告)号：US12150313B2

公开(公告)日：2024-11-19

申请号：US18500994

申请日：2023-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  I-Fan Chang ,  Rai-Min Huang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H01L23/522 ,  H01L23/528 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.