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    LAYOUT OF SEMICONDUCTOR MEMORY DEVICE
    41.
    发明公开
    LAYOUT OF SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230197153A1

    公开(公告)日：2023-06-22

    申请号：US17580591

    申请日：2022-01-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Yen Tseng ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Hsien Huang ,  Hsin-Chih Yu ,  Meng-Ping Chuang ,  Li-Ping Huang ,  Yu-Fang Chen

    IPC: G11C15/04

    CPC classification number: G11C15/04

    Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

    TERNARY CONTENT ADDRESSABLE MEMORY AND TWO-PORT STATIC RANDOM ACCESS MEMORY
    43.
    发明申请
    TERNARY CONTENT ADDRESSABLE MEMORY AND TWO-PORT STATIC RANDOM ACCESS MEMORY 有权

    公开(公告)号：US20220238158A1

    公开(公告)日：2022-07-28

    申请号：US17179418

    申请日：2021-02-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Yen Tseng ,  Chun-Chieh Chang

    IPC: G11C15/04

    Abstract: A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.

    Six-transistor static random access memory cell and operation method thereof
    47.
    发明授权
    Six-transistor static random access memory cell and operation method thereof 有权

    公开(公告)号：US10020049B1

    公开(公告)日：2018-07-10

    申请号：US15413436

    申请日：2017-01-24

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Chih-Wei Tsai

    IPC: G11C11/419 ,  G11C11/418

    Abstract: The present invention provides a six transistor static random-access memory (6T-SRAM) cell, the 6T-SRAM cell includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, and a first storage node, a second inverter comprising a second pull-up transistor, a second pull-down transistor, and a second storage node, wherein the first storage node is coupled to gates of the second pull-up transistor and the second pull-down transistor, a switch transistor configured to couple the second storage node to gates of the first pull-up transistor and the first pull-down transistor, and an access transistor coupled to gates of the first pull-up transistor and the first pull-down transistor.

    STATIC RANDOM-ACCESS MEMORY (SRAM) CELL ARRAY
    50.
    发明申请
    STATIC RANDOM-ACCESS MEMORY (SRAM) CELL ARRAY 审中-公开

    公开(公告)号：US20170373073A1

    公开(公告)日：2017-12-28

    申请号：US15686169

    申请日：2017-08-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

    IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/6681 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/785

    Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

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