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    Substantially enzyme free personal wash compositions comprising non-silicates with basal layer cationic charge
    44.
    发明申请
    Substantially enzyme free personal wash compositions comprising non-silicates with basal layer cationic charge 失效
    基本上无酶的个人洗涤组合物，其包含具有基础层阳离子电荷的非硅酸盐

    公开(公告)号：US20060025319A1

    公开(公告)日：2006-02-02

    申请号：US10902202

    申请日：2004-07-29

    申请人： Vivek Subramanian ,  Pravin Shah ,  Kavssery Ananthapadmanabhan

    发明人： Vivek Subramanian ,  Pravin Shah ,  Kavssery Ananthapadmanabhan

    IPC分类号： A61K8/00

    CPC分类号： A61K8/26 ,  A61Q19/10

    摘要： The present invention relates to personal wash compositions comprising, non-silicate particles, wherein the basal layer(s) carries a net cationic charge. The use of these specific particles results in enhanced properties (e.g., enhanced foaming, hydrotroping) of the personal wash products. The invention further discloses process for decreasing viscosity and/or increasing foam comprising formulating compositions with non-silicate layer compounds as specified.

    摘要翻译： 本发明涉及包含非硅酸盐颗粒的个人洗涤组合物，其中基底层承载净阳离子电荷。 这些特定颗粒的使用导致个人洗涤产品的增强的性能（例如，增强的起泡，水解加工）。 本发明进一步公开了降低粘度和/或增加泡沫的方法，其中包括按照规定的非硅酸盐层化合物配制组合物。

    Low cost three-dimensional memory array
    45.
    发明授权
    Low cost three-dimensional memory array 有权
    低成本三维存储阵列

    公开(公告)号：US06515888B2

    公开(公告)日：2003-02-04

    申请号：US09928969

    申请日：2001-08-13

    申请人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  P. Michael Farmwald ,  N. Johan Knall

    发明人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  P. Michael Farmwald ,  N. Johan Knall

    IPC分类号： G11C1100

    CPC分类号： H01L27/101 ,  G11C17/16 ,  H01L27/0688

    摘要： A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019/cm3), and wherein the read current is large (up to 500 mA).

    摘要翻译： 低成本存储单元阵列包括多个垂直堆叠的存储单元层。 在一种形式中，每个存储单元的特征在于小的横截面积和小于6.3微安培的读取电流。 所得到的存储器阵列具有缓慢的访问时间，并且非常适合于数字媒体存储，其中访问时间要求低，并且与所公开的存储器阵列相关联的显着的成本降低特别有吸引力。 在另一种形式中，每个存储器单元包括反熔丝层和二极管部件，其中至少一个二极管部件被重掺杂（掺杂浓度大于1019 / cm3），并且其中读取电流大（高达500mA）。

    Integrated circuit structure including three-dimensional memory array
    47.
    发明授权
    Integrated circuit structure including three-dimensional memory array 有权
    集成电路结构包括三维存储阵列

    公开(公告)号：US06385074B1

    公开(公告)日：2002-05-07

    申请号：US09748816

    申请日：2000-12-22

    申请人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

    发明人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

    IPC分类号： G11C1700

    CPC分类号： H01L27/1021 ,  G11C11/5692 ,  G11C17/14 ,  G11C17/16 ,  G11C2213/71 ,  H01L27/0203 ,  H01L27/115

    摘要： An integrated circuit device includes a three-dimensional memory array and array terminal circuitry for providing to selected memory cells of the array a write voltage different from a read voltage. Neither voltage is necessarily equal to a VDD power supply voltage supplied to the integrated circuit. The write voltage, particularly if greater than VDD, may be generated by an on-chip voltage generator, such as a charge pump, which may require an undesirably large amount of die area, particularly relative to a higher bit density three-dimensional memory array formed entirely in layers above a semiconductor substrate. In several preferred embodiments, the area directly beneath a memory array is advantageously utilized to layout at least some of the write voltage generator, thus locating the generator near the selected memory cells during a write operation.

    摘要翻译： 集成电路器件包括三维存储器阵列和阵列端子电路，用于向阵列的选定存储单元提供不同于读取电压的写入电压。 两个电压都不一定等于提供给集成电路的VDD电源电压。 特别是如果大于VDD的写入电压可以由片上电压发生器（例如电荷泵）产生，其可能需要不期望的大量管芯面积，特别是相对于较高位密度的三维存储器阵列 完全以半导体衬底上的层形成。 在几个优选实施例中，存储器阵列正下方的区域有利地用于布置写入电压发生器中的至少一些，从而在写入操作期间将发生器定位在选定的存储器单元附近。

    SYSTEMS AND METHODS FOR PROVIDING WIRELESS ASYMMETRIC NETWORK ARCHITECTURES OF WIRELESS DEVICES WITH POWER MANAGEMENT FEATURES
    49.
    发明申请
    SYSTEMS AND METHODS FOR PROVIDING WIRELESS ASYMMETRIC NETWORK ARCHITECTURES OF WIRELESS DEVICES WITH POWER MANAGEMENT FEATURES 有权
    提供具有电源管理功能的无线设备的无线非对称网络架构的系统和方法

    公开(公告)号：US20160219516A1

    公开(公告)日：2016-07-28

    申请号：US14607048

    申请日：2015-01-27

    申请人： Vivek Subramanian ,  Elad Alon ,  Vikram Pavate

    发明人： Vivek Subramanian ,  Elad Alon ,  Vikram Pavate

    IPC分类号： H04W52/02 ,  H04L5/14 ,  H04L12/44

    CPC分类号： H04W52/0219 ,  H04L12/44 ,  H04L2012/445 ,  Y02D70/00 ,  Y02D70/1224 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/162 ,  Y02D70/164 ,  Y02D70/22

    摘要： Systems and methods for implementing power management features while providing a wireless asymmetric network are disclosed herein. In one embodiment, a system includes a hub having a wireless control device that is configured to control communications and power consumption in the wireless asymmetric network architecture and sensor nodes each having at least one sensor and a wireless device with a transmitter and a receiver to enable bi-directional communications with the wireless control device of the hub. The wireless control device is configured to determine a scheduled timing of operating each sensor node during a first time period that is close in time with respect to a transmit window of the transmitter and during a second time period that is close in time with respect to a receive window of the receiver for each wireless device to reduce power consumption of the wireless devices of the sensor nodes.

    摘要翻译： 本文公开了在提供无线非对称网络的同时实现电力管理特征的系统和方法。 在一个实施例中，系统包括具有无线控制设备的集线器，无线控制设备被配置为控制无线非对称网络架构中的通信和功耗，每个传感器节点具有至少一个传感器和具有发射机和接收机的无线设备，以使能 与集线器的无线控制设备的双向通信。 无线控制设备被配置为确定在相对于发射机的发射窗口在时间上接近的第一时间段期间以及在相对于发射机的时间接近的第二时间段期间操作每个传感器节点的调度定时 接收每个无线设备的接收窗口，以减少传感器节点的无线设备的功耗。

    Method for configuring end-to-end lower order ODU network trails across optical transport network
    50.
    发明授权
    Method for configuring end-to-end lower order ODU network trails across optical transport network 有权
    在光传输网络上配置端到端低阶ODU网络路径的方法

    公开(公告)号：US09191115B2

    公开(公告)日：2015-11-17

    申请号：US13982491

    申请日：2011-07-07

    申请人： Nishant Sharma ,  Nikhil Satyarthi ,  Vivek Subramanian

    发明人： Nishant Sharma ,  Nikhil Satyarthi ,  Vivek Subramanian

    IPC分类号： H04J3/16 ,  H04L12/43 ,  H04B10/27

    CPC分类号： H04B10/27 ,  H04J3/1652 ,  H04J2203/0091

    摘要： The disclosure relates to a method of configuring end-to-end ODUj (lower order ODU) network trails across OTN (Optical Transport Network), in which the tributary port number (TPN) of the lower order ODUj inside higher order ODUk is specified. The time-slot value associated with the TPN is not to be specified by the user. The time-slots are dynamically allocated on the transmit side. On the receive side, there would be a capability in the ODUk adaptation sink function to find the set of time-slots associated with the TPN based on the received multiplex structure identifier (MSI). That is for an ODUj entity with a fixed TPN, the transmitted time-slots can change and the receive end can detect this change and based on that de-multiplex the ODUj from the ODUk.

    摘要翻译： 本发明涉及一种在OTN（Optical Transport Network，光传输网络）上配置端到端ODUj（低阶ODU）网络路径的方法，其中规定了高阶ODUk内的低阶ODUj的支路端口号（TPN）。 与TPN相关联的时隙值不被用户指定。 时隙在发送端动态分配。 在接收端，ODUk自适应接收功能将有能力基于所接收的多路复用结构标识符（MSI）找到与TPN相关联的时隙集合。 这是针对具有固定TPN的ODUj实体，所发送的时隙可以改变，并且接收端可以检测到该改变，并且基于从ODUk去除多路复用ODUj。