公开(公告)号：US06413802B1

公开(公告)日：2002-07-02

申请号：US09695532

申请日：2000-10-23

申请人： Chenming Hu ,  Tsu-Jae King ,  Vivek Subramanian ,  Leland Chang ,  Xuejue Huang ,  Yang-Kyu Choi ,  Jakub Tadeusz Kedzierski ,  Nick Lindert ,  Jeffrey Bokor ,  Wen-Chin Lee

发明人： Chenming Hu ,  Tsu-Jae King ,  Vivek Subramanian ,  Leland Chang ,  Xuejue Huang ,  Yang-Kyu Choi ,  Jakub Tadeusz Kedzierski ,  Nick Lindert ,  Jeffrey Bokor ,  Wen-Chin Lee

IPC分类号： H01L2100

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： A FinFET device is fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity. In one embodiment two transistors can be stacked in a fin to provide a CMOS transistor pair having a shared gate.

摘要翻译： FinFET器件采用传统的平面MOSFET技术制造。 器件制造在覆盖绝缘层（例如SIMOX）的硅层中，器件从绝缘层延伸为翅片。 在通道的两侧设置双门，以提供增强的驱动电流，并有效抑制短路效应。 可以在源极和漏极之间提供多个通道以增加电流容量。 在一个实施例中，两个晶体管可以堆叠在鳍中以提供具有共享栅极的CMOS晶体管对。

公开(公告)号：US08426927B2

公开(公告)日：2013-04-23

申请号：US13107783

申请日：2011-05-13

申请人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

发明人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

IPC分类号： H01L29/66 ,  H01L21/02

CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

摘要翻译： 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

公开(公告)号：US20120235274A1

公开(公告)日：2012-09-20

申请号：US13047656

申请日：2011-03-14

申请人： Brian S. Doyle ,  Charles C. Kuo ,  Nick Lindert ,  Uday Shah ,  Satyarth Suri ,  Robert S. Chau

发明人： Brian S. Doyle ,  Charles C. Kuo ,  Nick Lindert ,  Uday Shah ,  Satyarth Suri ,  Robert S. Chau

IPC分类号： H01L29/94 ,  H01L21/02

CPC分类号： H01L27/10894 ,  H01L27/10817 ,  H01L27/10855 ,  H01L28/91

摘要： Semiconductor structures having integrated double-wall capacitors for eDRAM and methods to form the same are described. For example, an embedded double-wall capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. The trench has a bottom and sidewalls. A U-shaped metal plate is disposed at the bottom of the trench, spaced apart from the sidewalls. A second dielectric layer is disposed on and conformal with the sidewalls of the trench and the U-shaped metal plate. A top metal plate layer is disposed on and conformal with the second dielectric layer.

摘要翻译： 描述了具有用于eDRAM的集成双壁电容器的半导体结构及其形成方法。 例如，嵌入式双壁电容器包括设置在设置在基板上方的第一电介质层中的沟槽。 沟槽有一个底部和侧壁。 U形金属板设置在沟槽的底部，与侧壁间隔开。 第二电介质层设置在沟槽和U形金属板的侧壁上并与其一致。 顶部金属板层设置在第二介电层上并与第二介质层保形。

公开(公告)号：US07427775B2

公开(公告)日：2008-09-23

申请号：US11789338

申请日：2007-04-24

申请人： Anand Murthy ,  Justin K. Brask ,  Andrew N. Westmeyer ,  Boyan Boyanov ,  Nick Lindert

发明人： Anand Murthy ,  Justin K. Brask ,  Andrew N. Westmeyer ,  Boyan Boyanov ,  Nick Lindert

IPC分类号： H01L29/06

CPC分类号： H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： The mobility of carriers may be increased in strained channel epitaxial source/drain transistors. Doped silicon material may be blanket deposited after removing ion implanted source/drain regions. The blanket deposition forms amorphous films over non-source/drain areas and crystalline films in source/drain regions. By using an etch which is selective to amorphous silicon, the amorphous material may be removed. This may avoid some problems associated with selective deposition of the doped silicon material.

摘要翻译： 在应变通道外延源/漏极晶体管中，载流子的迁移率可能会增加。 在去除离子注入的源极/漏极区之后，掺杂的硅材料可以被覆盖。 覆盖沉积在非源极/漏极区域和源极/漏极区域中形成晶体膜形成非晶态膜。 通过使用对非晶硅有选择性的蚀刻，可以去除非晶材料。 这可以避免与掺杂硅材料的选择性沉积相关的一些问题。

公开(公告)号：US20070145495A1

公开(公告)日：2007-06-28

申请号：US11319815

申请日：2005-12-27

申请人： Giuseppe Curello ,  Sivakumar Mudanai ,  Nick Lindert ,  Leonard Pipes ,  M. Shaheed ,  Sunit Tyagi

发明人： Giuseppe Curello ,  Sivakumar Mudanai ,  Nick Lindert ,  Leonard Pipes ,  M. Shaheed ,  Sunit Tyagi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823481 ,  H01L21/823412

摘要： A method including forming a transistor structure structure comprising a gate electrode over an active region of a substrate, the active region defined by a trench isolation structure and changing a performance of a narrow width transistor with respect to a wide width transistor by introducing a dopant into the active region adjacent an interface defined by the trench isolation structure and the gate electrode. A structure including a gate electrode formed on a substrate, an active region adjacent an interface defined by a trench isolation structure and a gate electrode and an implant within the active region to change a performance of a transistor.

摘要翻译： 一种包括在衬底的有源区上形成包括栅电极的晶体管结构结构的方法，所述有源区由沟槽隔离结构限定，并且通过将掺杂剂引入到宽宽度晶体管中来改变窄宽晶体管的性能 邻接由沟槽隔离结构和栅电极限定的界面的有源区。 一种结构，包括形成在衬底上的栅电极，与由沟槽隔离结构限定的界面相邻的有源区和栅电极以及有源区内的注入以改变晶体管的性能。

公开(公告)号：US20060046399A1

公开(公告)日：2006-03-02

申请号：US10925566

申请日：2004-08-25

申请人： Nick Lindert ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau ,  Mark Bohr ,  Anand Murthy

发明人： Nick Lindert ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau ,  Mark Bohr ,  Anand Murthy

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

摘要： A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.

摘要翻译： 栅极结构可以用作掩模以形成源区和漏区。 然后可以去除栅极结构以形成间隙，并且可以在间隙中形成间隔物以限定沟槽。 在将沟槽形成衬底的过程中，去除源极漏极区的一部分。 然后用外延材料填充衬底，并在其上形成新的栅极结构。 结果，可以实现更突然的源极漏极结。

公开(公告)号：US06946350B2

公开(公告)日：2005-09-20

申请号：US10750158

申请日：2003-12-31

申请人： Nick Lindert ,  Justin K. Brask

发明人： Nick Lindert ,  Justin K. Brask

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/045 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7848

摘要： Numerous embodiments of a method for highly selective faceting of the S/D regions in a CMOS device are described. In one embodiment, source/drain regions are formed on a substrate. The source/drain regions are wet etched to form faceted regions. A silicon germanium layer is formed on the faceted regions of the source/drain regions to yield a strained device.

摘要翻译： 描述了用于CMOS器件中的S / D区域的高选择性刻面的方法的许多实施例。 在一个实施例中，源极/漏极区域形成在衬底上。 源极/漏极区域被湿蚀刻以形成刻面区域。 在源极/漏极区的多面区域上形成硅锗层以产生应变器件。

公开(公告)号：US20050087801A1

公开(公告)日：2005-04-28

申请号：US10692696

申请日：2003-10-24

申请人： Nick Lindert ,  Anand Murthy ,  Justin Brask

发明人： Nick Lindert ,  Anand Murthy ,  Justin Brask

IPC分类号： H01L21/336 ,  H01L31/119

CPC分类号： H01L29/66628 ,  H01L29/66636

摘要： An epitaxially deposited source/drain extension may be formed for a metal oxide semiconductor field effect transistor. A sacrificial layer may be formed and etched away to undercut under the gate electrode. Then a source/drain extension of epitaxial silicon may be deposited to extend under the edges of the gate electrode. As a result, the extent by which the source/drain extension extends under the gate may be controlled by controlling the etching of the sacrificial material. Its thickness and depth may be controlled by controlling the deposition process. Moreover, the characteristics of the source/drain extension may be controlled independently of those of the subsequently formed deep or heavily doped source/drain junction.

摘要翻译： 可以为金属氧化物半导体场效应晶体管形成外延沉积的源极/漏极延伸。 可以形成牺牲层并蚀刻掉在栅电极下方的底切。 然后，可以沉积外延硅的源极/漏极延伸部，以在栅电极的边缘下延伸。 结果，可以通过控制牺牲材料的蚀刻来控制源极/漏极延伸在栅极下延伸的程度。 其厚度和深度可以通过控制沉积过程来控制。 此外，可以独立于后续形成的深度或重掺杂源极/漏极结的特性来控制源极/漏极延伸的特性。

公开(公告)号：US09691839B2

公开(公告)日：2017-06-27

申请号：US13996494

申请日：2011-12-14

申请人： Nick Lindert ,  Timothy E. Glassman ,  Andre Baran

发明人： Nick Lindert ,  Timothy E. Glassman ,  Andre Baran

IPC分类号： H01L27/108 ,  H01L49/02

CPC分类号： H01L28/40 ,  H01L27/108 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/90

摘要： Metal-insulator-metal (MIM) capacitors with insulator stacks having a plurality of metal oxide layers are described. For example, a MIM capacitor for a semiconductor device includes a trench disposed in a dielectric layer disposed above a substrate. A first metal plate is disposed along the bottom and sidewalls of the trench. An insulator stack is disposed above and conformal with the first metal plate. The insulator stack includes a first metal oxide layer having a first dielectric constant and a second metal oxide layer having a second dielectric constant. The first dielectric constant is higher than the second dielectric constant. The MIM capacitor also includes a second metal plate disposed above and conformal with the insulator stack.

公开(公告)号：US20130292797A1

公开(公告)日：2013-11-07

申请号：US13977542

申请日：2011-12-21

申请人： Nick Lindert ,  Kanwal Jit Singh ,  Byung-Chan Lee

发明人： Nick Lindert ,  Kanwal Jit Singh ,  Byung-Chan Lee

IPC分类号： H01L27/06 ,  H01L21/768

CPC分类号： H01L27/0611 ,  H01L21/76841 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/5223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Fully encapsulated conductive lines are generally described. For example, a first dielectric layer is formed on a substrate. Copper wiring is disposed below a top surface of the first dielectric layer. A barrier metal layer is formed over the copper wiring, the barrier metal layer flush with the top surface of the first dielectric layer, and a second dielectric layer is formed on the barrier metal layer and the top surface of the first dielectric layer. Other embodiments are also disclosed and claimed.

摘要翻译： 通常描述完全封装的导电线。 例如，在基板上形成第一电介质层。 铜布线设置在第一介电层的顶表面下方。 在铜布线上形成阻挡金属层，阻挡金属层与第一电介质层的顶表面齐平，并且在阻挡金属层和第一介电层的顶表面上形成第二电介质层。 还公开并要求保护其他实施例。