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公开(公告)号：US07079096B2
公开(公告)日：2006-07-18
申请号：US10253570
申请日：2002-09-24
申请人： Hajime Washio , Yasuyoshi Kaise , Kazuhiro Maeda , Yasushi Kubota
发明人： Hajime Washio , Yasuyoshi Kaise , Kazuhiro Maeda , Yasushi Kubota
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G3/3614 , G09G3/3688 , G09G2310/0248
摘要： Before a potential of counter electrode is changed, a potential holding circuit fixedly holds potentials of data signal lines S during a non-selective period of scanning signal lines G. This prevents the potentials of the data signal lines S from being an undesirably large potential, which is caused by coupling capacitors between the counter electrode and each data signal line S, whereby it is possible to supply to the pixel capacitor an electric charge corresponding to a gradation to be displayed, by using the relatively low potentials of the data signal lines S. This lowers a power supply voltage of a data signal driving circuit SD, thus reducing the electric power consumption. In short, with this arrangement, a liquid crystal display device can perform an opposed AC drive for line-inversion drive, frame-inversion drive and the like, by low power supply voltage of the data signal line driving circuit SD, thereby reducing the electric power consumption.
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公开(公告)号：US07071912B2
公开(公告)日：2006-07-04
申请号：US10631731
申请日：2003-08-01
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3677
摘要： A display panel drive circuit and a display panel are provided which are simple in structure but free from initial failure leading to impossibility to perform scanning. The display panel drive circuit of the present invention is structured such that thin film transistors constituting a signal input circuit connected to a circuit outside the display panel are formed in a structure having a dielectric breakdown strength higher than those of thin film transistors constituting other circuits. Specifically, countermeasures are taken by transistor formation in multi-gate structure, gate width broadening, resistance insertion between an input terminal and a transistor or the like. In the present invention, the circuit to which signals are externally inputted or thin film transistors of the same circuit is structured to withstand high voltage, thereby preventing the transistors from being deteriorated by high voltage and occurrence of initial failure while being simple in structure.
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公开(公告)号：US06940500B2
公开(公告)日：2005-09-06
申请号：US10252497
申请日：2002-09-23
申请人： Hajime Washio , Yasuyoshi Kaise , Kazuhiro Maeda , Yasushi Kubota
发明人： Hajime Washio , Yasuyoshi Kaise , Kazuhiro Maeda , Yasushi Kubota
CPC分类号： G09G3/3648 , G09G3/3688 , G09G2310/0248 , G09G2330/021
摘要： A potential of a data signal line S during a scanning period is charged to a substantially intermediate potential of a data signal at a corresponding frame. Thus, extremely large dispersion does not occur in a potential of each pixel capacitor with respect to a potential of the data signal line S, so that it is possible to restrict dispersion of a leak current flowing via an active element of each pixel. Thus, potential variation of a pixel PIX is reduced, so that it is possible to improve display quality during a non-scanning period. That is, in an active-matrix-type liquid crystal display, when a frame frequency is reduced by setting the non-scanning period to be sufficiently larger than a scanning period while a standby image is being displayed so as to realize low power consumption, the display quality is improved.
摘要翻译： 扫描周期期间的数据信号线S的电位被充电到相应帧的数据信号的大致中间电位。 因此，相对于数据信号线S的电位，每个像素电容器的电位不会发生极大的色散，从而可以限制流过每个像素的有源元件的漏电流的色散。 因此，像素PIX的电位变化减小，使得可以在非扫描期间提高显示质量。 也就是说，在有源矩阵型液晶显示器中，当通过在显示待机图像的同时将非扫描周期设置为比扫描周期充分大来降低帧频，从而实现低功耗， 显示质量得到提高。
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公开(公告)号：US20050008753A1
公开(公告)日：2005-01-13
申请号：US10496984
申请日：2002-11-19
IPC分类号： A23C9/152 , A23F3/16 , A23F3/18 , A23F5/24 , A23F5/26 , A23G1/00 , A23G1/30 , A23L1/221 , A23L1/30 , A23L2/02 , A23L2/04 , A23L2/38 , C12C1/00
CPC分类号： A23L2/04 , A23F3/18 , A23F5/26 , A23F5/265 , A23F5/267 , A23L2/38 , A23L27/10 , A23L27/11 , A23L33/105
摘要： A food objective for extraction and/or squeezing is charged into a colloid mill or a twin-screw extruder; immediately after and/or while milling, a low-temperature solvent (for example, water or milk of from −3 to 50° C.) is added; and after treating the food using the extruder, grounds are removed to produce an extract and/or a squeezed liquid. After milling objective foods, for example, a single product or a combination of foods such as coffee, green tea, black tea, herb tea, wild grass tea, Chinese medical tea, cocoa, vanilla, fruit, and vegetable, extraction and/or squeezing can be rapidly and extremely efficiently carried out at a low temperature, which is appropriate for the mass and continuous production. Furthermore, in comparison with the conventional employed extraction and/or squeezing methods such as a low-temperature extraction method which leads to deterioration in flavor due to oxidation after milling, etc. and requires a long time, the present invention brings effects extremely advantageous from the viewpoints of enhancement of flavor and economy. For example, in tea based drinks, a useful component suspends, whereby a vivid color tone inherent to each tea is kept over a long time.
摘要翻译： 将用于萃取和/或挤压的食品物料装入胶体磨或双螺杆挤出机中; 在研磨之后和/或碾磨时，加入低温溶剂（例如，水或牛奶-3至50℃）; 并且在使用挤出机处理食物之后，除去土壤以产生提取物和/或挤压液体。 在研磨客观食物之后，例如，单一产品或咖啡，绿茶，红茶，草本茶，野草，中医茶，可可，香草，水果和蔬菜等食品的组合，提取和/或 可以在适合于质量和连续生产的低温下快速且极其有效地进行挤压。 此外，与常规使用的提取和/或挤压方法相比，例如导致由于碾磨后的氧化导致的风味劣化等而需要较长时间的低温提取方法，本发明带来了非常有益的效果 增强风味和经济性的观点。 例如，在茶基饮料中，有用的成分悬浮，由此可以长时间保持每种茶固有的生动色调。
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公开(公告)号：US06724361B1
公开(公告)日：2004-04-20
申请号：US09703918
申请日：2000-11-01
申请人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
发明人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
IPC分类号： G09G336
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2310/0289
摘要： In a shift register provided with flip-flops that operate in synchronism with a clock signal, and a switching means, which is opened and closed in response to an output of the preceding stage of each of the flip-flops, is installed. The clock signal is selectively inputted by the switching means, and the selected clock signal is inverted and used as a shift register output from each of the stages. An output pulse having the same width as the pulse of the clock signal is generated.
摘要翻译： 在设置有与时钟信号同步工作的触发器的移位寄存器中，并且响应于每个触发器的前级的输出而被打开和关闭的开关装置被安装。 时钟信号由切换装置选择性地输入，所选择的时钟信号被反相并用作从每个级输出的移位寄存器。 产生具有与时钟信号的脉冲相同宽度的输出脉冲。
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公开(公告)号：US06603455B1
公开(公告)日：2003-08-05
申请号：US09176193
申请日：1998-10-21
IPC分类号： G09G336
CPC分类号： G09G3/3688 , G09G3/3677
摘要： A display panel drive circuit and a display panel are provided which are simple in structure but free from initial failure leading to impossibility to perform scanning. The display panel drive circuit of the present invention is structured such that thin film transistors constituting a signal input circuit connected to a circuit outside the display panel are formed in a structure having a dielectric breakdown strength higher than those of thin film transistors constituting other circuits. Specifically, countermeasures are taken by transistor formation in multi-gate structure, gate width broadening, resistance insertion between an input terminal and a transistor or the like. In the present invention, the circuit to which signals are externally inputted or thin film transistors of the same circuit is structured to withstand high voltage, thereby preventing the transistors from being deteriorated by high voltage and occurrence of initial failure while being simple in structure.
摘要翻译： 提供了一种显示面板驱动电路和显示面板，其结构简单，但没有初始故障，导致不可能执行扫描。 本发明的显示面板驱动电路被构造成使得构成与显示面板外部的电路连接的信号输入电路的薄膜晶体管形成为具有高于构成其它电路的薄膜晶体管的介电击穿强度的结构。 具体地，通过多栅极结构中的晶体管形成，栅极宽度加宽，输入端子和晶体管之间的电阻插入等来采取对策。 在本发明中，外部输入信号的电路或同一电路的薄膜晶体管被构造为承受高电压，从而防止晶体管在结构简单的同时由于高电压和初始故障的发生而劣化。
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公开(公告)号：US06556162B2
公开(公告)日：2003-04-29
申请号：US09847661
申请日：2001-05-02
申请人： Michael James Brownlow , Graham Andrew Cairns , Catherine Rosinda Marie Armida Dachs , Hidehiko Yamashita , Yasushi Kubota , Hajime Washio
发明人： Michael James Brownlow , Graham Andrew Cairns , Catherine Rosinda Marie Armida Dachs , Hidehiko Yamashita , Yasushi Kubota , Hajime Washio
IPC分类号： H03M166
CPC分类号： H03M1/682 , G09G3/3688 , G09G2310/0248 , G09G2310/027 , H03M1/687 , H03M1/765 , H03M1/804
摘要： A digital-to-analog converter includes a first converter stage 1 for converting the m most significant bits of a k bit input signal to upper and lower voltage limits VL and VH by selecting the appropriate low impedance reference voltages. A second converter stage 2 performs a linear conversion of the n least significant bits of the k bit input within the voltage range defined by the voltage limits VL and VH. A precharging circuit including switches SW1 and SW2 disconnects the stage 2 from the load CLOAD, which is charged to the voltage limit VL during the precharge phase. The load is subsequently disconnected from the voltage limit VL and connected to the output of the stage 2 to complete charging of the load CLOAD to the converter output voltage.
摘要翻译： 数模转换器包括第一转换器级1，用于通过选择合适的低阻抗参考电压将k位输入信号的m个最高有效位转换为上限和下限电压极限VL和VH。 第二转换器级2在由电压限制VL和VH限定的电压范围内执行k位输入的n个最低有效位的线性转换。 包括开关SW1和SW2的预充电电路从负载CLOAD断开级2，负载CLOAD在预充电阶段期间被充电到电压极限VL。 负载随后与电压限制VL断开并连接到级2的输出，以完成负载CLOAD到转换器输出电压的充电。
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公开(公告)号：US06492972B1
公开(公告)日：2002-12-10
申请号：US09275261
申请日：1999-03-23
申请人： Yasushi Kubota , Tamotsu Sakai , Hajime Washio
发明人： Yasushi Kubota , Tamotsu Sakai , Hajime Washio
IPC分类号： G09G336
CPC分类号： G09G3/3688 , G09G2300/0408 , G09G2320/0209
摘要： A data signal line driving circuit which sequentially forms a plurality of sampling signals and continuously samples input signals to output such input signals, in response to the plurality of sampling signals, wherein the sampling signals respectively represent sampling periods thereof which are different from each other, and a pulse width of each of the sampling signals is prescribed to be small so that rising and falling of each of the sampling signals do not overlap each other.
摘要翻译： 数据信号线驱动电路，响应于多个采样信号顺次形成多个采样信号并连续采样输入信号以输出这些输入信号，其中采样信号分别表示彼此不同的采样周期， 并且将每个采样信号的脉冲宽度规定为较小，使得每个采样信号的上升和下降彼此不重叠。
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公开(公告)号：US06476637B1
公开(公告)日：2002-11-05
申请号：US09568892
申请日：2000-05-11
IPC分类号： H03K190175
CPC分类号： H03K3/356113
摘要： A voltage level shifter comprises an input stage in the form of cross-coupled source followers and an output stage in the form of an amplifier AMP, which may have single-ended or differential inputs. The source followers comprise the transistors M1 and M2 and the transistors M3 and M4. Differential inputs IN and !IN are connected to the gates of the transistors M2 and M4. A bias voltage is supplied to the gate of the transistor M1 from a node B to which the drain of the transistor M3 and the source of the transistor M4 are connected. Similarly, a bias voltage is supplied to the gate of the transistor M3 from a node A to which the drain of the transistor M1 and the source of the transistor M2 are connected.
摘要翻译： 电压电平移位器包括交叉耦合源跟随器形式的输入级和放大器AMP形式的输出级，其可以具有单端或差分输入。 源极跟随器包括晶体管M1和M2以及晶体管M3和M4。 差分输入IN和！IN连接到晶体管M2和M4的栅极。 从晶体管M3的漏极和晶体管M4的源极连接的节点B向晶体管M1的栅极提供偏置电压。 类似地，偏置电压从晶体管M1的漏极和晶体管M2的源极连接到的节点A提供给晶体管M3的栅极。
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公开(公告)号：US06262598B1
公开(公告)日：2001-07-17
申请号：US09517984
申请日：2000-03-03
IPC分类号： H03K190175
CPC分类号： G11C7/062 , H03K19/018521 , H03K19/018528 , H03K19/01855
摘要： A voltage level shifter comprises complementary transistors T1, T2 connected between a supply line vdd and an inverting input !IN. The gate of the transistor T1 is connected to a direct signal input IN whereas the gate of the transistor T2 receives a shifted version of the direct input signal from a source-follower comprising the transistors T3 and T4. The level shifter may also be embodied as a differential cross-coupled sense amplifier with the sources of the drain load transistors being crossed coupled to the differential inputs.
摘要翻译： 电压电平移位器包括连接在电源线vdd和反相输入端IN之间的互补晶体管T1，T2。 晶体管T1的栅极连接到直接信号输入IN，而晶体管T2的栅极接收来自包括晶体管T3和T4的源极跟随器的直接输入信号的偏移版本。 电平移位器还可以被实现为差分交叉耦合读出放大器，其中漏极负载晶体管的源极与差分输入交叉耦合。
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