公开(公告)号：US07449911B2

公开(公告)日：2008-11-11

申请号：US11729759

申请日：2007-03-29

申请人： Yi-Lung Cheng ,  Bi-Ling Liu ,  Chin-Chuang Peng ,  Chien-Shih Tsai ,  Hway-Chi Lin

发明人： Yi-Lung Cheng ,  Bi-Ling Liu ,  Chin-Chuang Peng ,  Chien-Shih Tsai ,  Hway-Chi Lin

IPC分类号： G01R31/26

CPC分类号： G01R31/2858

摘要： A method for testing integrated circuits includes forming a plurality of substantially identical first test structures, each comprising a first via structure connected to a first metal line, stress testing the plurality of first test structures to obtain a first plurality of failure times, and forming a plurality of substantially identical second test structures, each comprising a second via structure connected to a second metal line, wherein the second via structure has a substantially different reliability from the first via structure, and wherein the first metal line and the second metal line are substantially identical. The method further includes stress testing the plurality of second test structures to obtain a second plurality of failure times, and determining early failures of the plurality of first test structures and the plurality of second test structures.

摘要翻译： 一种用于测试集成电路的方法包括形成多个基本上相同的第一测试结构，每个第一测试结构包括连接到第一金属线的第一通孔结构，测试多个第一测试结构以获得第一多个故障时间，以及形成 多个基本上相同的第二测试结构，每个包括连接到第二金属线的第二通孔结构，其中第二通孔结构具有与第一通孔结构基本上不同的可靠性，并且其中第一金属线和第二金属线基本相同 相同。 该方法还包括对多个第二测试结构进行压力测试以获得第二多个故障时间，以及确定多个第一测试结构和多个第二测试结构的早期故障。

公开(公告)号：US20080184805A1

公开(公告)日：2008-08-07

申请号：US11729759

申请日：2007-03-29

申请人： Yi-Lung Cheng ,  BL Lin ,  CC Peng ,  C.S. Tsai ,  Hway-Chi Lin

发明人： Yi-Lung Cheng ,  BL Lin ,  CC Peng ,  C.S. Tsai ,  Hway-Chi Lin

IPC分类号： G01N3/00

CPC分类号： G01R31/2858

摘要： A method for testing integrated circuits includes forming a plurality of substantially identical first test structures, each comprising a first via structure connected to a first metal line, stress testing the plurality of first test structures to obtain a first plurality of failure times, and forming a plurality of substantially identical second test structures, each comprising a second via structure connected to a second metal line, wherein the second via structure has a substantially different reliability from the first via structure, and wherein the first metal line and the second metal line are substantially identical. The method further includes stress testing the plurality of second test structures to obtain a second plurality of failure times, and determining early failures of the plurality of first test structures and the plurality of second test structures.

摘要翻译： 一种用于测试集成电路的方法包括形成多个基本上相同的第一测试结构，每个第一测试结构包括连接到第一金属线的第一通孔结构，测试多个第一测试结构以获得第一多个故障时间，以及形成 多个基本上相同的第二测试结构，每个包括连接到第二金属线的第二通孔结构，其中第二通孔结构具有与第一通孔结构基本上不同的可靠性，并且其中第一金属线和第二金属线基本相同 相同。 该方法还包括对多个第二测试结构进行压力测试以获得第二多个故障时间，以及确定多个第一测试结构和多个第二测试结构的早期故障。

公开(公告)号：US20070166887A1

公开(公告)日：2007-07-19

申请号：US11333618

申请日：2006-01-17

申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

IPC分类号： H01L21/82

CPC分类号： H01L27/0203 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.

摘要翻译： 提供了一种生成半导体器件阵列布局的方法。 提供了第一布局，包括有源导电特征，围绕有源导电特征的边界区域以及除了有源导电特征和边界区域之外的开放区域。 提供了多个不同图案密度的虚拟模板，每个虚拟模板包括多个虚拟种子。 通过根据至少一个虚拟模板将假种子添加到开放区域来生成第二布局。

公开(公告)号：US20070158835A1

公开(公告)日：2007-07-12

申请号：US11332566

申请日：2006-01-12

申请人： Jian-Hong Lin ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Ta-Wei Lee ,  Chih-Tao Lin ,  Jyh-Kang Ting ,  Lee-Chung Lu

发明人： Jian-Hong Lin ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Ta-Wei Lee ,  Chih-Tao Lin ,  Jyh-Kang Ting ,  Lee-Chung Lu

IPC分类号： H01L23/48

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is disclosed for determining a size of an interconnect between a first and a second conductor respectively in two layers of an integrated circuit while scaling from a reference processing technology to a predetermined processing technology. The method comprises selecting a set of design rules for the conductors based on the predetermined processing technology, determining a length of a first side of a rectangular cross sectional area of the interconnect based on the design rules and a scaling rule for scaling such a length from the reference processing technology to the predetermined processing technology, and determining a length of a second side of the cross sectional area of the interconnect for compensating an increase of a resistance of the interconnect due to the scaling from the reference processing technology to the predetermined processing technology.

摘要翻译： 公开了一种用于在从参考处理技术缩放到预定处理技术的同时，分别在集成电路的两层中确定第一和第二导体之间的互连尺寸的方法。 该方法包括基于预定的处理技术来选择一组导体的设计规则，基于设计规则确定互连的矩形横截面积的第一侧的长度，以及用于缩放这种长度的缩放规则 将参考处理技术应用于预定处理技术，以及确定互连横截面积的第二侧的长度，以补偿由于从参考处理技术到预定处理技术的缩放而导致的互连电阻的增加 。

公开(公告)号：US07074701B2

公开(公告)日：2006-07-11

申请号：US10718881

申请日：2003-11-21

申请人： Yi-Lung Cheng ,  Shih-Chia Cheng

发明人： Yi-Lung Cheng ,  Shih-Chia Cheng

IPC分类号： H01L21/31

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76832

摘要： A method of forming an opening in a stack of insulator layers featuring an underlying etch stop layer comprised of a tri-layer insulator composite, has been developed. The tri-layer insulator composite comprised of a bottom silicon rich, silicon oxide layer and a top silicon nitride layer, is first formed on a conductive region of a semiconductor substrate. After deposition of overlying insulator layers a photoresist shape is used as a etch mask to allow the desired contact or via hole shape to be defined in the overlying insulator layers via a first phase of an anisotropic dry etch procedure, with the first phase of the dry etching procedure terminating at the top surface of the silicon nitride layer. An over etch procedure used to insure complete removal of overlying insulator layer from the surface of the tri-layer insulator composite, is next performed as a second phase of the anisotropic dry etch procedure. The high etch rate ratio of insulator layer to silicon nitride allows the over etch cycle to be successfully accomplished without risk to underlying materials. A third phase of the anisotropic dry etch procedure selectively removes the silicon nitride layer and subsequently selectively removes the silicon rich, silicon oxide layer without damage to the now exposed conductive region, resulting in definition of the desired contact or via hole openings in the stack of insulator layers.

摘要翻译： 已经开发了在堆叠的绝缘体层中形成开口的方法，其特征在于由三层绝缘体复合材料构成的下面的蚀刻停止层。 首先在半导体衬底的导电区域上形成由富硅底层，氧化硅层和顶部氮化硅层组成的三层绝缘体复合体。 在沉积上覆绝缘体层之后，使用光致抗蚀剂形状作为蚀刻掩模，以允许通过各向异性干蚀刻程序的第一阶段在上覆绝缘体层中限定所需的接触或通孔形状，其中第一相干燥 蚀刻过程终止于氮化硅层的顶表面。 接下来，进行用于确保从三层绝缘体复合材料的表面完全去除上覆绝缘体层的过蚀刻程序作为各向异性干蚀刻工艺的第二阶段。 绝缘体层与氮化硅的高蚀刻速率比允许成功地实现过蚀刻循环，而不会对下面的材料造成风险。 各向异性干蚀刻过程的第三阶段选择性地去除氮化硅层，随后选择性地除去富含硅的氧化硅层，而不损害现在暴露的导电区域，导致定义了堆叠中的所需接触或通孔开口 绝缘体层。

公开(公告)号：US20050205991A1

公开(公告)日：2005-09-22

申请号：US10801475

申请日：2004-03-16

申请人： Hsien-Wei Chen ,  Jiun-Lin Yeh ,  Shin-Puu Jeng ,  Yi-Lung Cheng

发明人： Hsien-Wei Chen ,  Jiun-Lin Yeh ,  Shin-Puu Jeng ,  Yi-Lung Cheng

IPC分类号： H01L21/3205 ,  H01L21/44 ,  H01L21/768 ,  H01L21/82 ,  H01L23/34 ,  H01L23/433 ,  H01L23/52 ,  H01L23/528 ,  H01L27/04

CPC分类号： H01L23/528 ,  H01L21/76834 ,  H01L21/76837 ,  H01L23/4334 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a method and system for heat dissipation in semiconductor devices. In one example, an integrated circuit semiconductor device includes a semiconductor substrate; one or more metallurgy layers connected to the semiconductor substrate, and each of the one or more metallurgy layers includes: one or more conductive lines; and one or more dummy structures between the one or more conductive lines and at least two of the one or more dummy structures are connected; and one or more dielectric layers between the one or more metallurgy layers.

摘要翻译： 本公开提供了一种用于半导体器件中散热的方法和系统。 在一个示例中，集成电路半导体器件包括半导体衬底; 连接到半导体衬底的一个或多个冶金层，并且所述一个或多个冶金层中的每一个包括：一个或多个导电线; 并且连接所述一个或多个导电线与所述一个或多个虚拟结构中的至少两个之间的一个或多个虚设结构; 以及一个或多个冶金层之间的一个或多个电介质层。