公开(公告)号：US20080184805A1

公开(公告)日：2008-08-07

申请号：US11729759

申请日：2007-03-29

申请人： Yi-Lung Cheng ,  BL Lin ,  CC Peng ,  C.S. Tsai ,  Hway-Chi Lin

发明人： Yi-Lung Cheng ,  BL Lin ,  CC Peng ,  C.S. Tsai ,  Hway-Chi Lin

IPC分类号： G01N3/00

CPC分类号： G01R31/2858

摘要： A method for testing integrated circuits includes forming a plurality of substantially identical first test structures, each comprising a first via structure connected to a first metal line, stress testing the plurality of first test structures to obtain a first plurality of failure times, and forming a plurality of substantially identical second test structures, each comprising a second via structure connected to a second metal line, wherein the second via structure has a substantially different reliability from the first via structure, and wherein the first metal line and the second metal line are substantially identical. The method further includes stress testing the plurality of second test structures to obtain a second plurality of failure times, and determining early failures of the plurality of first test structures and the plurality of second test structures.

摘要翻译： 一种用于测试集成电路的方法包括形成多个基本上相同的第一测试结构，每个第一测试结构包括连接到第一金属线的第一通孔结构，测试多个第一测试结构以获得第一多个故障时间，以及形成 多个基本上相同的第二测试结构，每个包括连接到第二金属线的第二通孔结构，其中第二通孔结构具有与第一通孔结构基本上不同的可靠性，并且其中第一金属线和第二金属线基本相同 相同。 该方法还包括对多个第二测试结构进行压力测试以获得第二多个故障时间，以及确定多个第一测试结构和多个第二测试结构的早期故障。

公开(公告)号：US07449911B2

公开(公告)日：2008-11-11

申请号：US11729759

申请日：2007-03-29

申请人： Yi-Lung Cheng ,  Bi-Ling Liu ,  Chin-Chuang Peng ,  Chien-Shih Tsai ,  Hway-Chi Lin

发明人： Yi-Lung Cheng ,  Bi-Ling Liu ,  Chin-Chuang Peng ,  Chien-Shih Tsai ,  Hway-Chi Lin

IPC分类号： G01R31/26

CPC分类号： G01R31/2858

摘要： A method for testing integrated circuits includes forming a plurality of substantially identical first test structures, each comprising a first via structure connected to a first metal line, stress testing the plurality of first test structures to obtain a first plurality of failure times, and forming a plurality of substantially identical second test structures, each comprising a second via structure connected to a second metal line, wherein the second via structure has a substantially different reliability from the first via structure, and wherein the first metal line and the second metal line are substantially identical. The method further includes stress testing the plurality of second test structures to obtain a second plurality of failure times, and determining early failures of the plurality of first test structures and the plurality of second test structures.

摘要翻译： 一种用于测试集成电路的方法包括形成多个基本上相同的第一测试结构，每个第一测试结构包括连接到第一金属线的第一通孔结构，测试多个第一测试结构以获得第一多个故障时间，以及形成 多个基本上相同的第二测试结构，每个包括连接到第二金属线的第二通孔结构，其中第二通孔结构具有与第一通孔结构基本上不同的可靠性，并且其中第一金属线和第二金属线基本相同 相同。 该方法还包括对多个第二测试结构进行压力测试以获得第二多个故障时间，以及确定多个第一测试结构和多个第二测试结构的早期故障。

公开(公告)号：US20050124151A1

公开(公告)日：2005-06-09

申请号：US10728215

申请日：2003-12-04

申请人： Yi-Lung Cheng ,  Ren-Haur Liu ,  Cheng-Hsiung Liu ,  Ying-Lang Wang ,  Hway-Chi Lin ,  Chien-Ming Chiu

发明人： Yi-Lung Cheng ,  Ren-Haur Liu ,  Cheng-Hsiung Liu ,  Ying-Lang Wang ,  Hway-Chi Lin ,  Chien-Ming Chiu

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02126 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76819

摘要： A method is disclosed for depositing a Black Diamond layer in a CVD chamber. Trimethylsilane, O2, and Ar are flowed into the chamber at 300° C. to 400° C. with an O2:Ar:trimethylsilane flow rate ratio that is preferably 1:1.5:6. The resulting low k dielectric layer is formed with a higher deposition rate than when Ar is omitted and has a k value of about 3 that increases only slightly in O2 plasma. A higher density, hardness, and tensile strength are achieved in the Black Diamond layer when Ar is included in the deposition process. The addition of Ar in the deposition maintains film thickness uniformity below 2% for a longer period so that PM cleaning operations are less frequent and affords a lower fluorocarbon plasma etch rate to enable improved trench depth control in a damascene scheme. A lower leakage current and higher breakdown voltage in achieved in the resulting metal interconnect.

摘要翻译： 公开了一种用于在CVD室中沉积黑金刚石层的方法。 三甲基硅烷O 2和Ar在300℃至400℃下以0:2:Ar:三甲基硅烷流速比流入室中，优选 1：1.5：6。 形成的低k电介质层的沉积速率高于省略Ar时的沉积速率，并且具有约3的K值仅在O 2等离子体中略微增加。 当在沉积过程中包含Ar时，在黑色金刚石层中获得较高的密度，硬度和拉伸强度。 沉积中Ar的添加将膜厚度均匀性维持在2％以下更长的时间，以便PM清洁操作较不频繁，并提供较低的氟碳等离子体蚀刻速率，从而能够改进镶嵌方案中的沟槽深度控制。 在所得到的金属互连中实现较低的漏电流和更高的击穿电压。

公开(公告)号：US06514673B2

公开(公告)日：2003-02-04

申请号：US09818962

申请日：2001-03-28

申请人： Hway-Chi Lin ,  Yu-Ku Lin ,  Wen-Pin Chang ,  Ying-Lang Wang

发明人： Hway-Chi Lin ,  Yu-Ku Lin ,  Wen-Pin Chang ,  Ying-Lang Wang

IPC分类号： G03F700

CPC分类号： B24B37/013 ,  B24B37/042 ,  B24B49/12 ,  H01L21/31053 ,  H01L21/76224

摘要： A simple method for calculating the optimum amount of HDP deposited material that needs to be removed during CMP (without introducing dishing) is described. This method derives from our observation of a linear relationship between the amount of material that needs to be removed in order to achieve full planarization and a quantity called “OD for CMP density”. The latter is defined as PA×(100−PS) where PA is the percentage of active area relative to the total wafer area and PS is the percentage of sub-areas relative to the total wafer area. The sub-areas are regions in the dielectric, above the active areas, that are etched out prior to CMP. Thus, once the materials have been characterized, the optimum CMP removal thickness is readily calculated for a wide range of different circuit implementations.

公开(公告)号：US06291872B1

公开(公告)日：2001-09-18

申请号：US09433255

申请日：1999-11-04

申请人： Ying-Lang Wang ,  Hway-Chi Lin ,  Jun Wu ,  Jowei Dun

发明人： Ying-Lang Wang ,  Hway-Chi Lin ,  Jun Wu ,  Jowei Dun

IPC分类号： H01L2900

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01L27/08

摘要： Vertical type structures for integrated circuit inductors are disclosed. These vertical type inductors include the single-loop type, the parallel-loop type and the screw type, which form three different embodiments in the present invention. In the first embodiment, three-dimensional type structures, a single-loop type is utilized as an integrated circuit inductor. This inductor structure is formed on a substrate and the axis of the structure is upright to the substrate. In another embodiment according to the present invention, a parallel-loop type structure for radio frequency (RF) integrated circuit inductor is provided. A screw type structure according to this invention is the third embodiment. It features an axis that is parallel to the surface of the substrate and threads into the semiconductor device.

摘要翻译： 公开了集成电路电感器的垂直型结构。 这些垂直型电感器包括在本发明中形成三个不同实施例的单环型，并联环型和螺旋型。 在第一实施例中，采用单环型的三维型结构作为集成电路电感器。 该电感器结构形成在基板上，并且该结构的轴线垂直于基板。 在根据本发明的另一实施例中，提供了一种用于射频（RF）集成电路电感器的并联环路结构。 根据本发明的螺杆型结构是第三实施例。 它具有平行于衬底表面并进入半导体器件的轴线。

公开(公告)号：US06232043B1

公开(公告)日：2001-05-15

申请号：US09318471

申请日：1999-05-25

申请人： Hway-Chi Lin ,  Yu-Ku Lin ,  Wen-Pin Chang ,  Ying-Lang Wang

发明人： Hway-Chi Lin ,  Yu-Ku Lin ,  Wen-Pin Chang ,  Ying-Lang Wang

IPC分类号： G03F700

CPC分类号： B24B37/013 ,  B24B37/042 ,  B24B49/12 ,  H01L21/31053 ,  H01L21/76224

摘要： A simple method for calculating the optimum amount of HDP deposited material that needs to be removed during CMP (without introducing dishing) is described. This method derives from our observation of a linear relationship between the amount of material that needs to be removed in order to achieve full planarization and a quantity called “OD for CMP density”. The latter is defined as PA×(100−PS) where PA is the percentage of active area relative to the total wafer area and PS is the percentage of sub-areas relative to the total wafer area. The sub-areas are regions in the dielectric, above the active areas, that are etched out prior to CMP. Thus, once the materials have been characterized, the optimum CMP removal thickness is readily calculated for a wide range of different circuit implementations.

摘要翻译： 描述了一种用于计算在CMP期间需要去除的HDP沉积材料的最佳量的简单方法（不引入凹陷）。 该方法来源于我们观察到需要去除的材料的量之间的线性关系以实现完全平坦化，并且称为“用于CMP密度的OD”。 后者被定义为PAx（100-PS），其中PA是相对于总晶片面积的有效面积的百分比，PS是相对于总晶片面积的子区域的百分比。 子区域是在CMP之前被蚀刻出的有源区域之上的电介质区域。 因此，一旦材料被表征，就可以很容易地计算各种不同电路实现的最佳CMP去除厚度。