公开(公告)号：US20080184805A1

公开(公告)日：2008-08-07

申请号：US11729759

申请日：2007-03-29

申请人： Yi-Lung Cheng ,  BL Lin ,  CC Peng ,  C.S. Tsai ,  Hway-Chi Lin

发明人： Yi-Lung Cheng ,  BL Lin ,  CC Peng ,  C.S. Tsai ,  Hway-Chi Lin

IPC分类号： G01N3/00

CPC分类号： G01R31/2858

摘要： A method for testing integrated circuits includes forming a plurality of substantially identical first test structures, each comprising a first via structure connected to a first metal line, stress testing the plurality of first test structures to obtain a first plurality of failure times, and forming a plurality of substantially identical second test structures, each comprising a second via structure connected to a second metal line, wherein the second via structure has a substantially different reliability from the first via structure, and wherein the first metal line and the second metal line are substantially identical. The method further includes stress testing the plurality of second test structures to obtain a second plurality of failure times, and determining early failures of the plurality of first test structures and the plurality of second test structures.

摘要翻译： 一种用于测试集成电路的方法包括形成多个基本上相同的第一测试结构，每个第一测试结构包括连接到第一金属线的第一通孔结构，测试多个第一测试结构以获得第一多个故障时间，以及形成 多个基本上相同的第二测试结构，每个包括连接到第二金属线的第二通孔结构，其中第二通孔结构具有与第一通孔结构基本上不同的可靠性，并且其中第一金属线和第二金属线基本相同 相同。 该方法还包括对多个第二测试结构进行压力测试以获得第二多个故障时间，以及确定多个第一测试结构和多个第二测试结构的早期故障。

公开(公告)号：US20050124151A1

公开(公告)日：2005-06-09

申请号：US10728215

申请日：2003-12-04

申请人： Yi-Lung Cheng ,  Ren-Haur Liu ,  Cheng-Hsiung Liu ,  Ying-Lang Wang ,  Hway-Chi Lin ,  Chien-Ming Chiu

发明人： Yi-Lung Cheng ,  Ren-Haur Liu ,  Cheng-Hsiung Liu ,  Ying-Lang Wang ,  Hway-Chi Lin ,  Chien-Ming Chiu

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02126 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76819

摘要： A method is disclosed for depositing a Black Diamond layer in a CVD chamber. Trimethylsilane, O2, and Ar are flowed into the chamber at 300° C. to 400° C. with an O2:Ar:trimethylsilane flow rate ratio that is preferably 1:1.5:6. The resulting low k dielectric layer is formed with a higher deposition rate than when Ar is omitted and has a k value of about 3 that increases only slightly in O2 plasma. A higher density, hardness, and tensile strength are achieved in the Black Diamond layer when Ar is included in the deposition process. The addition of Ar in the deposition maintains film thickness uniformity below 2% for a longer period so that PM cleaning operations are less frequent and affords a lower fluorocarbon plasma etch rate to enable improved trench depth control in a damascene scheme. A lower leakage current and higher breakdown voltage in achieved in the resulting metal interconnect.

摘要翻译： 公开了一种用于在CVD室中沉积黑金刚石层的方法。 三甲基硅烷O 2和Ar在300℃至400℃下以0:2:Ar:三甲基硅烷流速比流入室中，优选 1：1.5：6。 形成的低k电介质层的沉积速率高于省略Ar时的沉积速率，并且具有约3的K值仅在O 2等离子体中略微增加。 当在沉积过程中包含Ar时，在黑色金刚石层中获得较高的密度，硬度和拉伸强度。 沉积中Ar的添加将膜厚度均匀性维持在2％以下更长的时间，以便PM清洁操作较不频繁，并提供较低的氟碳等离子体蚀刻速率，从而能够改进镶嵌方案中的沟槽深度控制。 在所得到的金属互连中实现较低的漏电流和更高的击穿电压。

公开(公告)号：US07157367B2

公开(公告)日：2007-01-02

申请号：US10861149

申请日：2004-06-04

申请人： Hway Chi Lin ,  Yi-Lung Cheng ,  Chao-Hsiung Wang

发明人： Hway Chi Lin ,  Yi-Lung Cheng ,  Chao-Hsiung Wang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate is provided having semiconductor device structures formed in and on the substrate. The semiconductor device structures comprise conductor layers embedded in openings in dielectric layers having a dielectric constant of less than 4.5. The dielectric layer has a roughness between the dielectric and the conductor wherein the roughness of the dielectric layer divided by the thickness of a barrier layer underlying the conductor layer is 0 to 1. The integrated circuit structure is prepared for failure analysis by removing the low dielectric constant dielectric layers and exposing the conductor layers for further failure analysis by optical examination or scanning electron microscope (SEM).

摘要翻译： 提供了一种衬底，其具有形成在衬底中和衬底上的半导体器件结构。 半导体器件结构包括嵌入介电常数小于4.5的电介质层的开口中的导体层。 电介质层在电介质和导体之间具有粗糙度，其中介电层的粗糙度除以导体层下面的阻挡层的厚度为0-1。集成电路结构通过去除低电介质来制备用于故障分析 恒电介质层，并通过光学检查或扫描电子显微镜（SEM）暴露导体层进行进一步的故障分析。

公开(公告)号：US07449911B2

公开(公告)日：2008-11-11

申请号：US11729759

申请日：2007-03-29

申请人： Yi-Lung Cheng ,  Bi-Ling Liu ,  Chin-Chuang Peng ,  Chien-Shih Tsai ,  Hway-Chi Lin

发明人： Yi-Lung Cheng ,  Bi-Ling Liu ,  Chin-Chuang Peng ,  Chien-Shih Tsai ,  Hway-Chi Lin

IPC分类号： G01R31/26

CPC分类号： G01R31/2858

摘要： A method for testing integrated circuits includes forming a plurality of substantially identical first test structures, each comprising a first via structure connected to a first metal line, stress testing the plurality of first test structures to obtain a first plurality of failure times, and forming a plurality of substantially identical second test structures, each comprising a second via structure connected to a second metal line, wherein the second via structure has a substantially different reliability from the first via structure, and wherein the first metal line and the second metal line are substantially identical. The method further includes stress testing the plurality of second test structures to obtain a second plurality of failure times, and determining early failures of the plurality of first test structures and the plurality of second test structures.

摘要翻译： 一种用于测试集成电路的方法包括形成多个基本上相同的第一测试结构，每个第一测试结构包括连接到第一金属线的第一通孔结构，测试多个第一测试结构以获得第一多个故障时间，以及形成 多个基本上相同的第二测试结构，每个包括连接到第二金属线的第二通孔结构，其中第二通孔结构具有与第一通孔结构基本上不同的可靠性，并且其中第一金属线和第二金属线基本相同 相同。 该方法还包括对多个第二测试结构进行压力测试以获得第二多个故障时间，以及确定多个第一测试结构和多个第二测试结构的早期故障。

公开(公告)号：US07420277B2

公开(公告)日：2008-09-02

申请号：US10801475

申请日：2004-03-16

申请人： Hsien-Wei Chen ,  Jiun-Lin Yeh ,  Shin-Puu Jeng ,  Yi-Lung Cheng

发明人： Hsien-Wei Chen ,  Jiun-Lin Yeh ,  Shin-Puu Jeng ,  Yi-Lung Cheng

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/528 ,  H01L21/76834 ,  H01L21/76837 ,  H01L23/4334 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a method and system for heat dissipation in semiconductor devices. In one example, an integrated circuit semiconductor device includes a semiconductor substrate; one or more metallurgy layers connected to the semiconductor substrate, and each of the one or more metallurgy layers includes: one or more conductive lines; and one or more dummy structures between the one or more conductive lines and at least two of the one or more dummy structures are connected; and one or more dielectric layers between the one or more metallurgy layers.

摘要翻译： 本公开提供了一种用于半导体器件中散热的方法和系统。 在一个示例中，集成电路半导体器件包括半导体衬底; 连接到半导体衬底的一个或多个冶金层，并且所述一个或多个冶金层中的每一个包括：一个或多个导电线; 并且连接所述一个或多个导电线与所述一个或多个虚拟结构中的至少两个之间的一个或多个虚设结构; 以及一个或多个冶金层之间的一个或多个电介质层。

公开(公告)号：US20050112859A1

公开(公告)日：2005-05-26

申请号：US10718881

申请日：2003-11-21

申请人： Yi-Lung Cheng ,  Shih-Chia Cheng

发明人： Yi-Lung Cheng ,  Shih-Chia Cheng

IPC分类号： H01L21/31 ,  H01L21/311 ,  H01L21/44 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76832

摘要： A method of forming an opening in a stack of insulator layers featuring an underlying etch stop layer comprised of a tri-layer insulator composite, has been developed. The tri-layer insulator composite comprised of a bottom silicon rich, silicon oxide layer and a top silicon nitride layer, is first formed on a conductive region of a semiconductor substrate. After deposition of overlying insulator layers a photoresist shape is used as a etch mask to allow the desired contact or via hole shape to be defined in the overlying insulator layers via a first phase of an anisotropic dry etch procedure, with the first phase of the dry etching procedure terminating at the top surface of the silicon nitride layer. An over etch procedure used to insure complete removal of overlying insulator layer from the surface of the tri-layer insulator composite, is next performed as a second phase of the anisotropic dry etch procedure. The high etch rate ratio of insulator layer to silicon nitride allows the over etch cycle to be successfully accomplished without risk to underlying materials. A third phase of the anisotropic dry etch procedure selectively removes the silicon nitride layer and subsequently selectively removes the silicon rich, silicon oxide layer without damage to the now exposed conductive region, resulting in definition of the desired contact or via hole openings in the stack of insulator layers.

摘要翻译： 已经开发了在堆叠的绝缘体层中形成开口的方法，其特征在于由三层绝缘体复合材料构成的下面的蚀刻停止层。 首先在半导体衬底的导电区域上形成由富硅底层，氧化硅层和顶部氮化硅层组成的三层绝缘体复合体。 在沉积上覆绝缘体层之后，使用光致抗蚀剂形状作为蚀刻掩模，以允许通过各向异性干蚀刻程序的第一阶段在上覆绝缘体层中限定所需的接触或通孔形状，其中第一相干燥 蚀刻过程终止于氮化硅层的顶表面。 接下来，进行用于确保从三层绝缘体复合材料的表面完全去除上覆绝缘体层的过蚀刻程序作为各向异性干蚀刻工艺的第二阶段。 绝缘体层与氮化硅的高蚀刻速率比允许成功地实现过蚀刻循环，而不会对下面的材料造成风险。 各向异性干蚀刻过程的第三阶段选择性地去除氮化硅层，随后选择性地除去富含硅的氧化硅层，而不损害现在暴露的导电区域，导致定义了堆叠中的所需接触或通孔开口 绝缘体层。

公开(公告)号：US06713407B1

公开(公告)日：2004-03-30

申请号：US10284399

申请日：2002-10-29

申请人： Yi-Lung Cheng ,  Wen-Kung Cheng ,  Sez-An Wu ,  Yi-Lung Wang ,  Shin-Chi Lin

发明人： Yi-Lung Cheng ,  Wen-Kung Cheng ,  Sez-An Wu ,  Yi-Lung Wang ,  Shin-Chi Lin

IPC分类号： H01L2131

CPC分类号： H01L21/3185 ,  C23C16/0245 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76838

摘要： A method of depositing a plasma enhanced CVD metal nitride layer over an exposed copper surface in a semiconductor wafer manufacturing process to improve the metal nitride layer adhesion and to reduce copper hillock formation including providing a process surface which is an exposed copper surface; preheating the process surface; plasma sputtering the exposed copper surface in-situ to remove copper oxides; and, depositing a metal nitride layer in-situ according to a plasma enhanced CVD process at a selected deposition pressure to reduce plasma ion bombardment energy transfer and to suppress-copper hillock formation.

摘要翻译： 一种在半导体晶片制造工艺中在暴露的铜表面上沉积等离子体增强的CVD金属氮化物层的方法，以改善金属氮化物层的粘合性并减少铜的小丘形成，包括提供作为暴露的铜表面的工艺表面; 预热过程表面; 等离子体溅射暴露的铜表面以去除铜氧化物; 以及根据等离子体增强CVD工艺在选定的沉积压力下原位沉积金属氮化物层以减少等离子体离子轰击能量转移并抑制铜小丘形成。

公开(公告)号：US06703317B1

公开(公告)日：2004-03-09

申请号：US10356248

申请日：2003-01-30

申请人： Yi-Lung Cheng ,  Ming-Hwa Yoo ,  Sze-An Wu ,  Ying-Lung Wang

发明人： Yi-Lung Cheng ,  Ming-Hwa Yoo ,  Sze-An Wu ,  Ying-Lung Wang

IPC分类号： H01L21302

CPC分类号： H01L21/3105 ,  H01L21/02052 ,  H01L21/76826 ,  H01L21/76837 ,  Y10S438/906

摘要： A method of reducing an electrical charge imbalance on a wafer process surface including providing a semiconductor wafer having a process surface including an upper most first material layer; cleaning the process surface according to a wafer cleaning process including at least one of spraying and scrubbing to produce an electrical charge imbalance at the process surface; and, subjecting the process surface to a nitrogen containing plasma treatment to at least partially neutralize the electrical charge imbalance.

摘要翻译： 一种减少晶片工艺表面上的电荷不平衡的方法，包括提供具有包括最上面的第一材料层的工艺表面的半导体晶片; 根据包括喷射和洗涤中的至少一种的晶片清洁过程清洁工艺表面以在工艺表面产生电荷不平衡; 并且使所述工艺表面进行含氮等离子体处理以至少部分地中和所述电荷不平衡。

公开(公告)号：US06479098B1

公开(公告)日：2002-11-12

申请号：US09747135

申请日：2000-12-26

申请人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： C23C1640

CPC分类号： H01J37/32477 ,  C23C16/4404 ,  Y10T428/2495 ,  Y10T428/265

摘要： A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the chamber plasma processing region components. An FSG layer is formed over the first USG layer. A second USG layer is formed over the FSG layer. Wherein the USG, FSG, and second USG layers comprise a UFU season film. A UFU season film coating the chamber plasma processing region components of a processing chamber comprises: an inner USG layer over the chamber plasma processing region components; an FSG layer over the inner USG layer; and an outer USG layer over the FSG layer.

摘要翻译： 一种用于减少具有室等离子体处理区域部件的处理室10中的污染物的方法，包括以下步骤。 腔室等离子体处理区域部件被清洁。 然后如下调节室。 在室等离子体处理区域部件上形成第一USG层。 在第一USG层上形成FSG层。 在FSG层上形成第二个USG层。 其中USG，FSG和第二USG层包括UFU季电影。 UFU季涂膜处理室的室等离子体处理区域部件包括：室上的内部USG层等离子体处理区域部件; 内部USG层上的FSG层; 以及FSG层上的外部USG层。

公开(公告)号：US07512924B2

公开(公告)日：2009-03-31

申请号：US11333618

申请日：2006-01-17

申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

IPC分类号： G06F17/50

CPC分类号： H01L27/0203 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.

摘要翻译： 提供了一种生成半导体器件阵列布局的方法。 提供了第一布局，包括有源导电特征，围绕有源导电特征的边界区域以及除了有源导电特征和边界区域之外的开放区域。 提供了多个不同图案密度的虚拟模板，每个虚拟模板包括多个虚拟种子。 通过根据至少一个虚拟模板将假种子添加到开放区域来生成第二布局。