公开(公告)号：US06344994B1

公开(公告)日：2002-02-05

申请号：US09795849

申请日：2001-02-28

Applicant: Darlene G. Hamilton ,  Yider Wu ,  Michael Han

Inventor： Darlene G. Hamilton ,  Yider Wu ,  Michael Han

IPC: G11C1604

CPC classification number: G11C16/3409 ,  G11C5/063 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3454

Abstract: Dummy wordlines are provided between gaps of blocks of memory cells to compensate for higher charge loss at higher stress temperatures exhibited at edge wordlines of blocks of memory cells having large gaps. The dummy wordlines minimize the gap between the blocks. The dummy wordlines can be positioned between the blocks. Alternatively, the wordline width for the last block or sector wordline can be changed or different nitride used with less conductance in high temperatures. The dummy wordlines are typically ignored in normal operations on the memory.

Abstract translation: 在存储单元块的间隙之间提供虚拟字线以补偿在具有大间隙的存储器单元的块的边缘字线处表现的较高应力温度下的较高电荷损失。 虚拟字线最小化块之间的差距。 虚拟字线可以位于块之间。 或者，可以改变最后一个块或扇区字线的字线宽度，或者在高温下以较小的电导率使用不同的氮化物。 通常在内存的正常操作中忽略伪字线。

公开(公告)号：US08759894B1

公开(公告)日：2014-06-24

申请号：US11189765

申请日：2005-07-27

Applicant: Yider Wu ,  Hiroyuki Ogawa ,  Unsoon Kim ,  Angela T. Hui

Inventor： Yider Wu ,  Hiroyuki Ogawa ,  Unsoon Kim ,  Angela T. Hui

IPC: H01L29/78

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/66833

Abstract: A memory device is provided including a substrate. A first dielectric layer is formed over the substrate. An isolation trench is formed in a portion of the substrate and the first dielectric layer. At least two charge storage elements are formed over the first dielectric layer on opposite sides of the isolation trench. A second dielectric layer is formed over the at least two charge storage elements. A control gate layer is formed over the second dielectric layer, where the isolation trench has a width suitable for reducing cross-coupling noise of charge storage elements, and where the at least two charge storage elements have a height suitable for providing sufficient gate coupling between the at least two charge storage elements and the control gate layer.

Abstract translation: 提供了包括基板的存储器件。 第一电介质层形成在衬底上。 在衬底和第一介电层的一部分中形成隔离沟槽。 在隔离沟槽的相对侧上的第一介电层上形成至少两个电荷存储元件。 在所述至少两个电荷存储元件上形成第二电介质层。 控制栅极层形成在第二介电层上，其中隔离沟槽具有适于减小电荷存储元件的交叉耦合噪声的宽度，并且其中至少两个电荷存储元件具有适于提供足够的栅极耦合的高度 所述至少两个电荷存储元件和所述控制栅极层。

公开(公告)号：US08647969B1

公开(公告)日：2014-02-11

申请号：US13362899

申请日：2012-01-31

Applicant: Rinji Sugino ,  Yider Wu ,  Minh Van Ngo ,  Jeffrey Sinclair Glick ,  Kuo Tung Chang

Inventor： Rinji Sugino ,  Yider Wu ,  Minh Van Ngo ,  Jeffrey Sinclair Glick ,  Kuo Tung Chang

IPC: H01L21/20

CPC classification number: H01L21/02532 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.

Abstract translation: 一种制造存储器件的方法包括在衬底上形成第一介电层，在第一介电层上形成电荷存储元件，并在电荷存储元件上形成栅极间电介质。 该方法还包括使用含氯的反应物在栅极间电介质上沉积硅控制栅极层。

公开(公告)号：US20120094450A1

公开(公告)日：2012-04-19

申请号：US12907077

申请日：2010-10-19

Applicant: Yider Wu ,  Sheng-Da Liu

Inventor： Yider Wu ,  Sheng-Da Liu

IPC: H01L21/336

CPC classification number: H01L29/66825 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/7881

Abstract: A manufacturing method of a multi-level cell NOR flash memory includes the steps of forming a memory cell area and a peripheral circuit area with the same depth of a shallow trench isolation structure, and the depth ranges from 2400 Å to 2700 Å; forming a non-self-aligned gate structure; performing a self-alignment source manufacturing process; and forming a common source area and a plurality of drain areas. The manufacturing method achieves a high integration density between components and provides a better thermal budget and a better dosage control to the multi-level cell NOR flash memory to improve the production yield rate.

Abstract translation: 多级单元NOR闪速存储器的制造方法包括以下步骤：形成具有与浅沟槽隔离结构相同深度的存储单元区域和外围电路区域，并且深度范围从2400到2700A; 形成非自对准栅极结构; 执行自对准源制造过程; 以及形成公共源极区域和多个漏极区域。 该制造方法实现了组件之间的高集成度密度，为多级单元NOR闪存提供了更好的热预算和更好的剂量控制，从而提高了生产率。

公开(公告)号：US08133801B1

公开(公告)日：2012-03-13

申请号：US11189875

申请日：2005-07-27

Applicant: Rinji Sugino ,  Yider Wu ,  Minh Van Ngo ,  Jeffrey Sinclair Glick ,  Kuo-Tung Chang

Inventor： Rinji Sugino ,  Yider Wu ,  Minh Van Ngo ,  Jeffrey Sinclair Glick ,  Kuo-Tung Chang

IPC: H01L21/20

CPC classification number: H01L21/02532 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.

Abstract translation: 一种制造存储器件的方法包括在衬底上形成第一介电层，在第一介电层上形成电荷存储元件，并在电荷存储元件上形成栅极间电介质。 该方法还包括使用含氯的反应物在栅极间电介质上沉积硅控制栅极层。

公开(公告)号：US20110230028A1

公开(公告)日：2011-09-22

申请号：US12728348

申请日：2010-03-22

Applicant: Yider Wu ,  Hung-Wei Chen

Inventor： Yider Wu ,  Hung-Wei Chen

IPC: H01L21/8234

CPC classification number: H01L27/11521 ,  H01L27/11519

Abstract: In a manufacturing method of a straight word line NOR flash memory array, a source line is implanted after the formation of a word line in the NOR type flash memory array is completed, and a discrete implant region is formed in the NOR type flash memory array and parallel to a component isolation structure, and each discrete implant region constitutes an electric connection with a low impedance between a source line and source contacts on the source line. With such discrete distribution, adjacent memory cells will not be short-circuited or failed even if a deviation of a mash occurs during the manufacturing process.

Abstract translation: 在直线NOR闪存阵列的制造方法中，在NOR型闪速存储器阵列中形成字线之后植入源极线，并且在NOR型闪存阵列中形成离散的注入区域 并且平行于部件隔离结构，并且每个离散注入区域构成源极线和源极线上的源极触点之间具有低阻抗的电连接。 通过这种离散分布，即使在制造过程中发生醪液的偏差，相邻的存储单元也不会短路或失效。

公开(公告)号：US08017488B2

公开(公告)日：2011-09-13

申请号：US12562870

申请日：2009-09-18

Applicant: Sheng-Da Liu ,  Yider Wu

Inventor： Sheng-Da Liu ,  Yider Wu

IPC: H01L21/336

CPC classification number: H01L21/26513 ,  H01L29/66825 ,  H01L29/7881 ,  Y10S438/914

Abstract: A manufacturing method of a NOR flash memory with phosphorous and arsenic ion implantations mainly implants both phosphorous and arsenic ions on a drain area of a transistor memory unit, and controls specific energy and dosage for the implantation to reduce the defects of a memory device and improve the yield rate of the NOR flash memory.

Abstract translation: 具有磷和砷离子注入的NOR闪存的制造方法主要在晶体管存储器单元的漏极区域上植入磷和砷离子，并且控制用于注入的比能量和剂量以减少存储器件的缺陷并改善 NOR闪存的收益率。

公开(公告)号：US08008692B2

公开(公告)日：2011-08-30

申请号：US12233486

申请日：2008-09-18

Applicant: Hung-Wei Chen ,  Yider Wu

Inventor： Hung-Wei Chen ,  Yider Wu

IPC: H01L29/04

CPC classification number: H01L29/7881 ,  H01L29/42324 ,  H01L29/7843

Abstract: A semiconductor memory structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zone to yield stress different in level; a barrier plug separating the two device zones from each other; and a plurality of oxide spacers being located between the first stress regions and the barrier plug while in direct contact with the first stress regions. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and only a relatively lower reading voltage is needed to obtain an initially required reading current. As a result, the probability of stress-induced leakage current is reduced to enhance the data retention ability.

Abstract translation: 具有应力区域的半导体存储器结构包括限定第一和第二器件区的衬底; 形成在第一和第二装置区域中的每一个中的第一和第二应力区域以产生不同水平的应力; 将两个装置区彼此分开的阻挡塞; 并且多个氧化物间隔物位于第一应力区域和阻挡塞之间，同时与第一应力区域直接接触。 由于在应力区产生的应力，载流子迁移率增加，因此可以获得增加的读取电流，并且仅需要相对较低的读取电压以获得最初需要的读取电流。 结果，减小了应力诱发漏电流的概率，提高了数据保留能力。

公开(公告)号：US20100065893A1

公开(公告)日：2010-03-18

申请号：US12233486

申请日：2008-09-18

Applicant: Hung-Wei Chen ,  Yider Wu

Inventor： Hung-Wei Chen ,  Yider Wu

IPC: H01L29/04

CPC classification number: H01L29/7881 ,  H01L29/42324 ,  H01L29/7843

Abstract: A semiconductor memory structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zone to yield stress different in level; a barrier plug separating the two device zones from each other; and a plurality of oxide spacers being located between the first stress regions and the barrier plug while in direct contact with the first stress regions. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and only a relatively lower reading voltage is needed to obtain an initially required reading current. As a result, the probability of stress-induced leakage current is reduced to enhance the data retention ability.

Abstract translation: 具有应力区域的半导体存储器结构包括限定第一和第二器件区的衬底; 形成在第一和第二装置区域中的每一个中的第一和第二应力区域以产生不同水平的应力; 将两个装置区彼此分开的阻挡塞; 并且多个氧化物间隔物位于第一应力区域和阻挡塞之间，同时与第一应力区域直接接触。 由于在应力区产生的应力，载流子迁移率增加，因此可以获得增加的读取电流，并且仅需要相对较低的读取电压以获得最初需要的读取电流。 结果，减小了应力诱发漏电流的概率，提高了数据保留能力。

公开(公告)号：US07265014B1

公开(公告)日：2007-09-04

申请号：US10799413

申请日：2004-03-12

Applicant: Angela T. Hui ,  Jusuke Ogura ,  Yider Wu

Inventor： Angela T. Hui ,  Jusuke Ogura ,  Yider Wu

IPC: H01L21/764 ,  H01L29/00

CPC classification number: H01L21/76224

Abstract: A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI region and extend beyond the boundaries of the STI region. A portion of the ARC layer may be etched leaving a remaining portion of the ARC layer over the STI region and extending beyond the boundaries of the STI region. A protective cap may be deposited to cover the remaining portion of the ARC layer as well as the insulating material. The protective cap may be etched back to expose the ARC layer. However, the protective cap still covers and protects the insulating material. By providing a protective cap that covers the insulating material, gouging of the insulating material in STI regions may be avoided.

Abstract translation: 一种用于避免半导体器件的浅沟槽隔离（STI）区域中的氧化物气刨的方法和装置。 可以在STI区域中蚀刻沟槽并填充绝缘材料。 抗反射涂层（ARC）层可以沉积在STI区域上并延伸超出STI区域的边界。 可以蚀刻ARC层的一部分，留下ARC层的剩余部分超过STI区域并延伸超出STI区域的边界。 可以沉积保护盖以覆盖ARC层的剩余部分以及绝缘材料。 可以将保护盖回蚀以暴露ARC层。 然而，保护盖仍然覆盖并保护绝缘材料。 通过提供覆盖绝缘材料的保护帽，可以避免STI区域中的绝缘材料的气刨。