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    System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device
    1.
    发明授权
    System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device 有权
    用于减少半导体器件中的电荷存储元件之间的交叉耦合噪声的系统和方法

    公开(公告)号：US08759894B1

    公开(公告)日：2014-06-24

    申请号：US11189765

    申请日：2005-07-27

    申请人： Yider Wu ,  Hiroyuki Ogawa ,  Unsoon Kim ,  Angela T. Hui

    发明人： Yider Wu ,  Hiroyuki Ogawa ,  Unsoon Kim ,  Angela T. Hui

    IPC分类号： H01L29/78

    CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/66833

    摘要： A memory device is provided including a substrate. A first dielectric layer is formed over the substrate. An isolation trench is formed in a portion of the substrate and the first dielectric layer. At least two charge storage elements are formed over the first dielectric layer on opposite sides of the isolation trench. A second dielectric layer is formed over the at least two charge storage elements. A control gate layer is formed over the second dielectric layer, where the isolation trench has a width suitable for reducing cross-coupling noise of charge storage elements, and where the at least two charge storage elements have a height suitable for providing sufficient gate coupling between the at least two charge storage elements and the control gate layer.

    摘要翻译： 提供了包括基板的存储器件。 第一电介质层形成在衬底上。 在衬底和第一介电层的一部分中形成隔离沟槽。 在隔离沟槽的相对侧上的第一介电层上形成至少两个电荷存储元件。 在所述至少两个电荷存储元件上形成第二电介质层。 控制栅极层形成在第二介电层上，其中隔离沟槽具有适于减小电荷存储元件的交叉耦合噪声的宽度，并且其中至少两个电荷存储元件具有适于提供足够的栅极耦合的高度 所述至少两个电荷存储元件和所述控制栅极层。

    Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space
    2.
    发明授权
    Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space 有权
    非自对准浅沟槽隔离工艺与一次性空间定义亚光刻多孔空间

    公开(公告)号：US06664191B1

    公开(公告)日：2003-12-16

    申请号：US09973131

    申请日：2001-10-09

    申请人： Unsoon Kim ,  Yider Wu ,  Yu Sun ,  Michael K. Templeton ,  Angela T. Hui ,  Chi Chang

    发明人： Unsoon Kim ,  Yider Wu ,  Yu Sun ,  Michael K. Templeton ,  Angela T. Hui ,  Chi Chang

    IPC分类号： H01L21302

    CPC分类号： H01L27/11526 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76229 ,  H01L21/76838 ,  H01L27/11531 ,  Y10S438/975

    摘要： A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates of flash memory cells. STI regions are formed between adjacent memory cells in a substrate to isolate the cells from one another. The first polysilicon layer is deposited over the substrate covering the STI regions. The first polysilicon layer is then planarized by a CMP process or the like to eliminate overlay issues associated with the STI regions. A hard mask layer is deposited over the first polysilicon layer and a first space dimension d1 etched between adjacent memory cells. A conformal nitride layer is deposited over the hard mask layer and an etch step performed to form nitride side walls adjacent the spaces. The nitride side walls reduce the first space dimension to a second space dimension d2, so that spaces can be formed in the first polysilicon layer at a dimension smaller than the minimum printable dimension of the photolithographic tool set.

    摘要翻译： 提供了一种在光刻工具组的最小打印尺寸之下形成具有在存储器单元之间的空间的线的方法。 在本发明的一个方面，线和间隔形成在形成闪存单元的浮动栅极的第一多晶硅层中。 STI区域形成在衬底中的相邻存储单元之间，以隔离细胞。 第一多晶硅层沉积在覆盖STI区域的衬底上。 然后通过CMP工艺等将第一多晶硅层平坦化，以消除与STI区域相关联的覆盖问题。 在第一多晶硅层上沉积硬掩模层，并在相邻的存储单元之间蚀刻第一空间尺寸d1。 在硬掩模层上沉积共形氮化物层，并且执行蚀刻步骤以形成邻近空间的氮化物侧壁。 氮化物侧壁将第一空间尺寸减小到第二空间尺寸d2，使得可以以小于光刻工具组的最小可打印尺寸的尺寸在第一多晶硅层中形成空间。

    Avoiding field oxide gouging in shallow trench isolation (STI) regions
    5.
    发明授权
    Avoiding field oxide gouging in shallow trench isolation (STI) regions 有权
    在浅沟槽隔离（STI）区域避免场氧化物气刨

    公开(公告)号：US07265014B1

    公开(公告)日：2007-09-04

    申请号：US10799413

    申请日：2004-03-12

    申请人： Angela T. Hui ,  Jusuke Ogura ,  Yider Wu

    发明人： Angela T. Hui ,  Jusuke Ogura ,  Yider Wu

    IPC分类号： H01L21/764 ,  H01L29/00

    CPC分类号： H01L21/76224

    摘要： A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI region and extend beyond the boundaries of the STI region. A portion of the ARC layer may be etched leaving a remaining portion of the ARC layer over the STI region and extending beyond the boundaries of the STI region. A protective cap may be deposited to cover the remaining portion of the ARC layer as well as the insulating material. The protective cap may be etched back to expose the ARC layer. However, the protective cap still covers and protects the insulating material. By providing a protective cap that covers the insulating material, gouging of the insulating material in STI regions may be avoided.

    摘要翻译： 一种用于避免半导体器件的浅沟槽隔离（STI）区域中的氧化物气刨的方法和装置。 可以在STI区域中蚀刻沟槽并填充绝缘材料。 抗反射涂层（ARC）层可以沉积在STI区域上并延伸超出STI区域的边界。 可以蚀刻ARC层的一部分，留下ARC层的剩余部分超过STI区域并延伸超出STI区域的边界。 可以沉积保护盖以覆盖ARC层的剩余部分以及绝缘材料。 可以将保护盖回蚀以暴露ARC层。 然而，保护盖仍然覆盖并保护绝缘材料。 通过提供覆盖绝缘材料的保护帽，可以避免STI区域中的绝缘材料的气刨。

    Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device
    7.
    发明授权
    Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device 有权
    闪存器件的核心和周边区域内的STI（浅沟槽隔离）结构的形成

    公开(公告)号：US06509232B1

    公开(公告)日：2003-01-21

    申请号：US09969573

    申请日：2001-10-01

    申请人： Unsoon Kim ,  Mark S. Chang ,  Yider Wu ,  Chi Chang ,  Angela Hui ,  Yu Sun

    发明人： Unsoon Kim ,  Mark S. Chang ,  Yider Wu ,  Chi Chang ,  Angela Hui ,  Yu Sun

    IPC分类号： H01L21336

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536

    摘要： STI (shallow trench isolation) structures are formed for a flash memory device fabricated within an semiconductor substrate comprised of a core area having an array of core flash memory cells fabricated therein and comprised of a periphery area having logic circuitry fabricated therein. A first set of STI (shallow trench isolation) openings within the core area are etched through the semiconductor substrate, and a second set of STI (shallow trench isolation) openings within the periphery area are etched through the semiconductor substrate. A core active device area of the semiconductor substrate within the core area is surrounded by the first set of STI openings, and a periphery active device area of the semiconductor substrate within the periphery area is surrounded by the second set of STI openings. Dielectric liners are formed at sidewalls of the first and second sets of STI openings with reaction of the semiconductor substrate at the sidewalls of the STI openings such that top corners of the semiconductor substrate of the core and periphery active device areas adjacent the STI openings are rounded. A trench dielectric material is deposited to fill the STI openings. In addition, the top corners of the periphery active device area are exposed by etching portions of the sidewalls of the second set of STI structures in a dip-off etch. The exposed top corners of the periphery active device area are further rounded after additional thermal oxidation of the exposed top corners of the periphery active device area. The rounded corners of the core and periphery active device areas result in minimized leakage current through a flash memory cell fabricated within the core active device area and through a MOSFET fabricated within the periphery active device area.

    摘要翻译： 形成STI（浅沟槽隔离）结构，用于制造在半导体衬底内的闪存器件，该半导体衬底由具有在其中制造的核心闪存单元阵列的核心区域组成，并由其中制造的逻辑电路的外围区域组成。 核心区域内的第一组STI（浅沟槽隔离）开口被蚀刻穿过半导体衬底，并且外围区域内的第二组STI（浅沟槽隔离）开口被蚀刻穿过半导体衬底。 核心区域内的半导体衬底的核心有源器件区域由第一组STI开口包围，并且周边区域内的半导体衬底的外围有源器件区域被第二组STI开口包围。 电介质衬垫通过半导体衬底在STI开口的侧壁处的反应而形成在第一和第二组STI开口的侧壁处，使得芯部的半导体衬底和邻近STI开口的周边有源器件区域的顶角是圆形的 。 沉积沟槽电介质材料以填充STI开口。 此外，通过在浸渍蚀刻中蚀刻第二组STI结构的侧壁的部分来暴露外围有源器件区域的顶角。 外围有源器件区域的暴露的顶角在外围有源器件区域的暴露顶角的额外的热氧化之后被进一步倒圆。 核心和外围有源器件区域的圆角导致通过在核心有源器件区域内制造的闪存单元和通过在外围有源器件区域内制造的MOSFET的最小化的漏电流。

    System and method for improving reliability in a semiconductor device
    8.
    发明授权
    System and method for improving reliability in a semiconductor device 有权
    用于提高半导体器件的可靠性的系统和方法

    公开(公告)号：US08802537B1

    公开(公告)日：2014-08-12

    申请号：US11189874

    申请日：2005-07-27

    申请人： Yider Wu ,  Unsoon Kim ,  Kuo-Tung Chang ,  Harpreet Sachar

    发明人： Yider Wu ,  Unsoon Kim ,  Kuo-Tung Chang ,  Harpreet Sachar

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76224 ,  H01L21/02057

    摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The memory device is pre-cleaned to prepare a surface of the memory device for oxide formation thereon, where cleaning the memory device removes portions of the barrier oxide layer on opposite sides of the trench. The nitride layer is trimmed on opposite sides of the trench. A liner oxide layer is formed in the trench.

    摘要翻译： 提供了一种用于形成存储器件的方法。 在衬底上形成氮化物层。 蚀刻氮化物层和衬底以形成沟槽。 存储器件被预先清洁以准备用于其上形成氧化物的存储器件的表面，其中清洁存储器件去除沟槽相对侧上的阻挡氧化物层的部分。 在沟槽的相对侧上修整氮化物层。 在沟槽中形成衬里氧化物层。

    Hard mask removal process including isolation dielectric refill
    9.
    发明授权
    Hard mask removal process including isolation dielectric refill 有权
    硬掩模去除工艺包括隔离介质再填充

    公开(公告)号：US06607925B1

    公开(公告)日：2003-08-19

    申请号：US10165837

    申请日：2002-06-06

    申请人： Unsoon Kim ,  Dawn M. Hopper ,  Yider Wu ,  Krishnashree Achuthan

    发明人： Unsoon Kim ,  Dawn M. Hopper ,  Yider Wu ,  Krishnashree Achuthan

    IPC分类号： H01L2100

    CPC分类号： H01L21/76224 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/32139

    摘要： A method for repairing an isolation dielectric damaged during a semiconductor fabrication process is disclosed in which a hard mask material is used to pattern a first material, the first material having openings therein exposing isolation regions comprising a first isolation dielectric layer. The method includes etching the hard mask material from the first material, wherein the etch creates gouges in the first isolation dielectric layer, and depositing a second layer of isolation dielectric over the first material, wherein the second isolation dielectric layer fills the gouges in the first isolation dielectric layer. The method further includes polishing on the second layer of isolation dielectric to remove the second layer of isolation dielectric from the first material.

    摘要翻译： 公开了一种用于修复在半导体制造工艺期间损坏的隔离电介质的方法，其中使用硬掩模材料来图案化第一材料，其中在其中具有开口的第一材料暴露出包括第一隔离介电层的隔离区域。 该方法包括从第一材料蚀刻硬掩模材料，其中蚀刻在第一隔离电介质层中产生沟槽，以及在第一材料上沉积第二隔离电介质层，其中第二隔离电介质层填充第一隔离电介质层中的沟槽 隔离介电层。 该方法还包括在第二层隔离电介质上抛光以从第一材料去除第二隔离电介质层。

    Die seal for semiconductor device moisture protection
    10.
    发明授权
    Die seal for semiconductor device moisture protection 失效
    半导体器件防潮密封

    公开(公告)号：US06566736B1

    公开(公告)日：2003-05-20

    申请号：US09998624

    申请日：2001-11-30

    申请人： Hiroyuki Ogawa ,  Yider Wu ,  Yu Sun

    发明人： Hiroyuki Ogawa ,  Yider Wu ,  Yu Sun

    IPC分类号： H01L23544

    CPC分类号： H01L23/564 ,  H01L23/3185 ,  H01L23/485 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05567 ,  H01L2224/45144 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2224/05552 ,  H01L2924/00

    摘要： Moisture seal apparatus and methodologies are disclosed for protecting semiconductor devices from moisture. An upper seal layer, such as SiN is formed over an upper insulator layer and an exposed portion of a die seal metal structure so as to form a vertical moisture seal between electrical components in the semiconductor device and the ambient environment. A lateral seal may be formed from the die seal metal structure in an upper metal layer in the device and one or more contacts extending downward from the die seal metal to the substrate or to a lower die seal metal structure.

    摘要翻译： 公开了用于保护半导体器件免受湿气的湿度密封装置和方法。 在上绝缘体层和模具密封金属结构的暴露部分上形成诸如SiN的上密封层，以便在半导体器件中的电气部件和周围环境之间形成垂直的湿气密封。 横向密封件可以由装置中的上金属层中的模具密封金属结构和从模具密封金属向下延伸到基板或下模密封金属结构的一个或多个触点形成。