公开(公告)号：US07808032B2

公开(公告)日：2010-10-05

申请号：US12145681

申请日：2008-06-25

申请人： Yue-Song He ,  Len Mei

发明人： Yue-Song He ,  Len Mei

IPC分类号： H01L21/8247 ,  H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7854 ,  H01L29/7881

摘要： A floating gate memory cell's channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer. The narrow fin or other feature are then formed without further photolithography in areas between the adjacent spacers. More particularly, a third layer (340) is formed in these areas, and the first layer and the spacers are removed selectively to the third layer. The third layer is used as a mask to form the narrow features.

摘要翻译： 浮动栅极存储单元的沟道区域（104）至少部分地位于半导体衬底的鳍状突起（110P）中。 浮栅的顶面可以沿着突起的至少两侧下降到突起的顶部（110P-T）的下方。 控制门的底面也可能下降至低于突起顶部的水平。 浮动门的底面可能下降到突起顶部以下至少50％的高度。 将浮动栅极与突起分离的电介质（120）可以在突起的顶部处至少与在突起的顶部下方的突起高度的至少50％的水平（L2）相同。 存储器和非存储器集成电路中的非常狭窄的鳍或其他窄特征可以通过提供第一层（320）然后从第二层形成间隔物（330）而形成，而不需要在由第一层制成的特征的侧壁上进行光刻。 然后在相邻间隔物之间​​的区域中形成窄鳍片或其它特征，而无需进一步的光刻。 更具体地，在这些区域中形成第三层（340），并且第一层和间隔物被选择性地去除到第三层。 第三层用作掩模以形成窄特征。

公开(公告)号：US20090101961A1

公开(公告)日：2009-04-23

申请号：US11876557

申请日：2007-10-22

申请人： Yue-Song He ,  Len Mei

发明人： Yue-Song He ,  Len Mei

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： The present disclosure provides a memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, a tantalum-nitride layer, and a control gate layer. When a positive bias is applied to the control gate and the select gate, negative charges are injected from a channel region of a substrate through the tunneling dielectric layer and into the charge storage layer to thereby store the negative charges in the charge storage layer. When a negative bias is applied to the control gate, negative charges are tunneled from the charge storage layer to the channel region of the substrate through the tunneling dielectric layer.

摘要翻译： 本公开提供了一种存储器件，其具有与单元堆叠相邻形成的单元堆叠和选择栅极。 电池堆包括隧道介电层，电荷存储层，阻挡介电层，氮化钽层和控制栅层。 当向控制栅极和选择栅极施加正偏压时，从衬底的沟道区域通过隧道电介质层注入负电荷并进入电荷存储层，从而将负电荷存储在电荷存储层中。 当向控制栅极施加负偏压时，负电荷通过隧道电介质层从电荷存储层隧穿到衬底的沟道区。

公开(公告)号：US07511333B2

公开(公告)日：2009-03-31

申请号：US11246447

申请日：2005-10-06

申请人： Yue-Song He ,  Chung Wai Leung ,  Jin-Ho Kim ,  Kwok Kwok Ng

发明人： Yue-Song He ,  Chung Wai Leung ,  Jin-Ho Kim ,  Kwok Kwok Ng

IPC分类号： H01L27/115 ,  H01L29/66

CPC分类号： H01L29/42336 ,  G11C16/0458 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521

摘要： A memory cell (110) has a plurality of floating gates (120L, 120R). The channel region (170) comprises a plurality of sub-regions (220L, 220R) adjacent to the respective floating gates, and a connection region (210) between the floating gates. The connection region has the same conductivity type as the source/drain regions (160) to increase the channel conductivity. Therefore, the floating gates can be brought closer together even though the inter-gate dielectric (144) becomes thick between the floating gates, weakening the control gate's (104) electrical field in the channel.

摘要翻译： 存储单元（110）具有多个浮动栅极（120L，120R）。 沟道区域（170）包括与相应浮动栅极相邻的多个子区域（220L，220R），以及浮置栅极之间的连接区域（210）。 连接区域具有与源极/漏极区域（160）相同的导电类型以增加沟道导电性。 因此，即使栅极间电介质（144）在浮置栅极之间变厚，削弱了沟道中的控制栅极（104）电场，浮动栅极也可以更靠近在一起。

公开(公告)号：US07084458B1

公开(公告)日：2006-08-01

申请号：US11120690

申请日：2005-05-02

申请人： Imran Khan ,  Jianshi Wang ,  Yue-Song He ,  Jun Kang

发明人： Imran Khan ,  Jianshi Wang ,  Yue-Song He ,  Jun Kang

IPC分类号： H01L29/76

CPC分类号： H01L29/665 ,  H01L29/66598

摘要： A method of fabricating a semiconductor device having a triple LDD (lateral diffused dopants) structure is disclosed. This fabrication method requires a single implant process, leading to reduction in fabrication costs and fabrication time. Moreover, this fabrication method increases the surface area of the gate structure of the semiconductor device that is available for silicide to be formed, leading to lower gate resistance.

摘要翻译： 公开了一种制造具有三重LDD（横向漫射掺杂剂）结构的半导体器件的方法。 这种制造方法需要单个注入工艺，导致制造成本和制造时间的降低。 此外，该制造方法增加可用于要形成的硅化物的半导体器件的栅极结构的表面积，导致较低的栅极电阻。

公开(公告)号：US07020021B1

公开(公告)日：2006-03-28

申请号：US10981833

申请日：2004-11-04

申请人： Wing-Han Leung ,  Richard M. Fastow ,  Yue-Song He ,  Sheung-Hee Park

发明人： Wing-Han Leung ,  Richard M. Fastow ,  Yue-Song He ,  Sheung-Hee Park

IPC分类号： G11C16/04

CPC分类号： G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3445 ,  G11C16/3468 ,  G11C16/3477

摘要： A method of erasing bits in a multi-level cell flash memory array is described. The method includes applying over-erase verification after each erase pulse. If cells verify as over-erased, a ramped over-erase correction pulse is applied. The voltage of each over-erase correction pulse is incrementally greater than the previous pulse, until all bits in all cells pass the over-erase verification. In this way, the widths of the threshold voltage distributions of the erased bits are kept to a minimum.

摘要翻译： 描述了擦除多级单元闪存阵列中的位的方法。 该方法包括在每个擦除脉冲之后应用过擦除验证。 如果电池验证为过擦除，则施加斜坡过擦除校正脉冲。 每个过擦除校正脉冲的电压递增地大于先前的脉冲，直到所有单元中的所有位通过过擦除验证。 以这种方式，擦除位的阈值电压分布的宽度保持最小。

公开(公告)号：US06963506B1

公开(公告)日：2005-11-08

申请号：US10679179

申请日：2003-10-03

申请人： Zhigang Wang ,  Nian Yang ,  Yue-Song He

发明人： Zhigang Wang ,  Nian Yang ,  Yue-Song He

IPC分类号： G11C16/06 ,  G11C16/26 ,  G11C16/30

CPC分类号： G11C16/30 ,  G11C16/26

摘要： An exemplary sensing circuit for sensing the current drawn by a target memory cell comprises a first transistor connected across a first node and a second node, a load connected across the second node and a third node, and a voltage boosting circuit coupled to a supply voltage, wherein the voltage boosting circuit supplies a voltage at the third node which is greater than the supply voltage.

摘要翻译： 用于感测由目标存储器单元汲取的电流的示例性感测电路包括跨越第一节点和第二节点连接的第一晶体管，跨过第二节点连接的负载和第三节点，以及耦合到电源电压的升压电路 ，其中所述升压电路在所述第三节点处提供大于所述电源电压的电压。

公开(公告)号：US06963106B1

公开(公告)日：2005-11-08

申请号：US10839626

申请日：2004-05-04

申请人： Richard Fastow ,  Yue-Song He ,  Kazuhiro Mizutani ,  Timothy Thurgate

发明人： Richard Fastow ,  Yue-Song He ,  Kazuhiro Mizutani ,  Timothy Thurgate

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing a dielectric material from an isolation region situated in a substrate to expose a trench, where the trench is situated between a first source region and a second source region, where the trench defines sidewalls in the substrate. The method further comprises implanting an N type dopant in the first source region, the second source region, and the sidewalls of the trench, where the N type dopant forms an N+ type region. The method further comprises implanting a P type dopant in the first source region, the second source region, and the sidewalls of the trench, where the P type dopant forms a P type region, and where the P type region is situated underneath the N+ type region.

摘要翻译： 根据一个示例性实施例，一种用于制造浮动栅极存储器阵列的方法包括从位于衬底中的隔离区域去除介电材料以暴露沟槽的步骤，其中沟槽位于第一源区域和第二源极之间 区域，其中沟槽限定衬底中的侧壁。 该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入N型掺杂剂，其中N型掺杂剂形成N +型区域。 该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入P型掺杂剂，其中P型掺杂剂形成P型区域，并且其中P型区域位于N +型下方 地区。

公开(公告)号：US06953752B1

公开(公告)日：2005-10-11

申请号：US10358756

申请日：2003-02-05

申请人： Yue-Song He ,  Sameer Haddad ,  Zhi-Gang Wang ,  Richard Fastow

发明人： Yue-Song He ,  Sameer Haddad ,  Zhi-Gang Wang ,  Richard Fastow

IPC分类号： H01L21/311 ,  H01L21/8247

CPC分类号： H01L27/11521

摘要： In the present method of undertaking a self aligned source etch of a semiconductor structure, a substrate has oxide thereon. First and second adjacent stacked gate structures are provided on the substrate. Oxide spacers are provided on the respective first and second adjacent sides of the first and second gate stacked structures, and polysilicon spacers are provided on the respective oxide spacers. A self aligned source etch is undertaken using the gate structures, oxide spacers, and polysilicon spacers as a mask. The polysilicon spacers are then removed, and metal, for example cobalt, is provided on the substrate, using the oxide spacers as a mask. A silicidation step is undertaken to form metal silicide common source line on the substrate.

摘要翻译： 在进行半导体结构的自对准源蚀刻的本方法中，衬底在其上具有氧化物。 第一和第二相邻的堆叠栅极结构设置在基板上。 在第一和第二栅极堆叠结构的相应的第一和第二相邻侧上设置氧化物间隔物，并且在各个氧化物间隔物上设置多晶硅间隔物。 使用栅极结构，氧化物间隔物和多晶硅间隔物作为掩模进行自对准源蚀刻。 然后去除多晶硅间隔物，并且使用氧化物间隔物作为掩模在衬底上提供金属（例如钴）。 进行硅化步骤以在衬底上形成金属硅化物共同源极线。

公开(公告)号：US06939770B1

公开(公告)日：2005-09-06

申请号：US10618514

申请日：2003-07-11

申请人： Imran Khan ,  Jianshi Wang ,  Yue-Song He ,  Jun Kang

发明人： Imran Khan ,  Jianshi Wang ,  Yue-Song He ,  Jun Kang

IPC分类号： H01L21/336

CPC分类号： H01L29/665 ,  H01L29/66598

摘要： A method of fabricating a semiconductor device having a triple LDD (lateral diffused dopants) structure is disclosed. This fabrication method requires a single implant process, leading to reduction in fabrication costs and fabrication time. Moreover, this fabrication method increases the surface area of the gate structure of the semiconductor device that is available for silicide to be formed, leading to lower gate resistance.

摘要翻译： 公开了一种制造具有三重LDD（横向漫射掺杂剂）结构的半导体器件的方法。 这种制造方法需要单个注入工艺，导致制造成本和制造时间的降低。 此外，该制造方法增加可用于要形成的硅化物的半导体器件的栅极结构的表面积，导致较低的栅极电阻。

公开(公告)号：US06939766B1

公开(公告)日：2005-09-06

申请号：US10616804

申请日：2003-07-09

申请人： Yue-Song He ,  Richard M. Fastow ,  Jianshi Wang

发明人： Yue-Song He ,  Richard M. Fastow ,  Jianshi Wang

IPC分类号： H01L21/28 ,  H01L21/8247

CPC分类号： H01L21/28273

摘要： The present invention is a method for fabricating a flash memory device. In one embodiment, a gate structure comprising a tunnel oxide layer, a floating gate layer, an oxide layer, and a control gate layer is fabricated on a semiconductor substrate. A rapid thermal oxidation (RTO) process is then performed to repair the tunnel oxide layer.

摘要翻译： 本发明是一种制造闪存装置的方法。 在一个实施例中，在半导体衬底上制造包括隧道氧化物层，浮动栅极层，氧化物层和控制栅极层的栅极结构。 然后进行快速热氧化（RTO）处理以修复隧道氧化物层。