公开(公告)号：US06473865B1

公开(公告)日：2002-10-29

申请号：US09272171

申请日：1999-03-18

申请人： Masahiro Kamoshida ,  Haruki Toda ,  Tsuneaki Fuse ,  Yukihito Oowaki

发明人： Masahiro Kamoshida ,  Haruki Toda ,  Tsuneaki Fuse ,  Yukihito Oowaki

IPC分类号： G06F112

CPC分类号： G06F1/3287 ,  G06F1/10 ,  G06F1/3203 ,  Y02D10/126 ,  Y02D10/171

摘要： Each delay unit is divided into two delay unit groups, the preceding stage side and the succeeding stage side. To the delay unit group in the preceding stage side, power supply voltage is supplied via a power supply terminal, and to each delay unit of the delay unit group in the succeeding stage side, power supply voltage is supplied from the power supply terminal via a power supply control switch. A forward-pulse detecting circuit detects that forward pulse was propagated to a stage between the N-th stage and a stage a predetermined number of stages before the N-th, and outputs the detected result to the power supply control switch. With this operation, when forward pulse is propagated to the (N+1)th stage, power supply voltage is supplied also to the delay unit group in the succeeding stage side. As electric power is not supplied to the delay unit group in the succeeding stage side when forward pulse is not propagated to the (N+1)th stage, wasteful consumption of electric power is prevented.

摘要翻译： 每个延迟单元被分成两个延迟单元组，即前级侧和后级侧。 对于前级侧的延迟单元组，经由电源端子向后级侧的延迟单元组的延迟单元供给电源电压，经由电源端子从电源端子供给电源电压 电源控制开关。 正向脉冲检测电路检测正向脉冲传播到第N级的第N级与预定级的级之间的级，并将检测结果输出到电源控制开关。 通过这种操作，当正向脉冲传播到第（N + 1）级时，电源电压也被提供给后级侧的延迟单元组。 当正向脉冲不传播到第（N + 1）级时，由于不向后级侧的延迟单元组提供电力，所以防止了浪费的电力消耗。

公开(公告)号：US06393080B1

公开(公告)日：2002-05-21

申请号：US09271329

申请日：1999-03-18

申请人： Masahiro Kamoshida ,  Haruki Toda ,  Tsuneaki Fuse ,  Yukihito Oowaki

发明人： Masahiro Kamoshida ,  Haruki Toda ,  Tsuneaki Fuse ,  Yukihito Oowaki

IPC分类号： H04L700

CPC分类号： G11C7/222 ,  G11C7/22 ,  H03K5/135 ,  H03L7/00 ,  H04L7/0337

摘要： A state-holding circuit initializing circuit initializes state-holding circuit when propagation of forward pulse to the forward-pulse delay circuits in the last stage is detected. With this operation, synchronization is established in a short time from the resumption of outputting from a receiver. The state-holding circuit control circuit also controls the reset timing of the state-holding circuit. A forward-pulse adjusting circuit controls the pulse width of forward pulse to be supplied to the forward-pulse delay line. With this operation, the stages from the stage where rearward pulse was generated to the first stage are securely turned to the set state, enabling propagation of rearward pulse and synchronization is established. Thus, synchronization is established reliably even when output from a receiver stops or the duty of an external clock signal is heavy.

摘要翻译： 状态保持电路初始化电路在正向脉冲传播到最后一级的正向脉冲延迟电路时，初始化状态保持电路。 通过该操作，从恢复从接收器输出的短时间内建立同步。 状态保持电路控制电路还控制状态保持电路的复位定时。 正向脉冲调整电路控制要提供给正向脉冲延迟线的正向脉冲的脉冲宽度。 通过该动作，从产生向后脉冲的阶段到第一阶段的阶段被牢固地转到设定状态，从而能够建立向后脉冲的传播和同步。 因此，即使从接收器的输出停止或外部时钟信号的占空比很重，也能够可靠地建立同步。

公开(公告)号：US06327654B1

公开(公告)日：2001-12-04

申请号：US09151774

申请日：1998-09-11

申请人： Yukihito Oowaki ,  Hiroshige Fujii ,  Hideo Shimizu ,  Takehisa Kato ,  Naoki Endo ,  Atsushi Masuda ,  Hiroaki Nishi ,  Kazunori Ohuchi ,  Masatoshi Sekine

发明人： Yukihito Oowaki ,  Hiroshige Fujii ,  Hideo Shimizu ,  Takehisa Kato ,  Naoki Endo ,  Atsushi Masuda ,  Hiroaki Nishi ,  Kazunori Ohuchi ,  Masatoshi Sekine

IPC分类号： G06F1130

CPC分类号： G06F21/72 ,  H04L9/0625 ,  H04L2209/08 ,  H04L2209/122 ,  H04L2209/125

摘要： A semiconductor integrated circuit for cryptographic process according to the present invention, comprises a randomizing unit for randomizing first input data which is one of two divided parts of input data based on configuration information to identify an algorithm in randomizing process, a function F portion for receiving data which have been subjected to the randomizing process and then applying coding process to the data, and an exclusive logical sum circuit for receiving second input data which is other of two divided parts of the input data and output data from the function F portion and then outputting an exclusive logical sum of the second input data and the output data.

摘要翻译： 根据本发明的用于密码处理的半导体集成电路包括：随机化单元，用于基于配置信息随机化作为输入数据的两个分割部分之一的第一输入数据，以识别随机化过程中的算法;函数F部分，用于接收 已经经过随机化处理然后对数据进行编码处理的数据，以及用于接收作为输入数据的两个分割部分中的另外两个部分的第二输入数据和来自功能F部分的输出数据的异或逻辑和电路， 输出第二输入数据和输出数据的异或逻辑和。

公开(公告)号：US6118721A

公开(公告)日：2000-09-12

申请号：US578900

申请日：1995-12-27

申请人： Yukihito Oowaki

发明人： Yukihito Oowaki

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1042 ,  G11C7/10 ,  G11C7/1033 ,  G11C7/1039 ,  G11C7/1072

摘要： A dynamic random access memory with two divided memory banks is disclosed wherein memory cells are divided into first and second groups each of which includes an array of memory cells connected to a corresponding word line. Those memory cells are subdivided into subgroups each of which has four memory cells. A first set of input/output lines is provided for the first group of memory cells, and a second set of input/output lines is provided for the second group of memory cells. An output circuit section is connected to the those sets of input/output lines to output data transferred thereto. An access controller section specifies subgroups alternately from the first and second groups of memory cells with four memory cells as a substantial access minimum unit, accesses memory cells of a specified subgroup to read stored data therefrom and transfers the read data to corresponding input/output lines associated therewith. The read data is supplied to the output circuit section for conversion to serial data and then output therefrom.

公开(公告)号：US6040610A

公开(公告)日：2000-03-21

申请号：US56632

申请日：1998-04-08

申请人： Mitsuhiro Noguchi ,  Yukihito Oowaki

发明人： Mitsuhiro Noguchi ,  Yukihito Oowaki

IPC分类号： H01L27/04 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H03K19/0944 ,  H01L29/72

CPC分类号： H01L27/092 ,  H01L21/8238 ,  H03K19/0027

摘要： A semiconductor device comprises a chip including a MISFET having a source and a drain, in which one of the source and the drain is connected to a second current supply node, an impedance element having a first terminal connected to the other of the source and the drain and a second terminal connected to a first current supply node, and a switching element, in which a well or a body electrode of the MISFET has an active state and a standby state, and is connected to a bias voltage generator for generating different voltages through the switching element, the threshold voltage V.sub.ths during standby state of the MISFET is higher than the threshold voltage V.sub.tha during active state of the MISFET, a voltage applied to a gate of the MISFET being able to take two stationary values, and the following relationship is satisfied V.sub.DD (1-V.sub.ths /V.sub.DD)

摘要翻译： 半导体器件包括芯片，其包括具有源极和漏极的MISFET，源极和漏极中的一个连接到第二电流源节点，阻抗元件具有连接到源极的另一个的第一端子和 漏极和连接到第一电流源节点的第二端子，以及开关元件，其中MISFET的阱或体电极具有活动状态和待机状态，并且连接到用于产生不同电压的偏置电压发生器 通过开关元件，MISFET的待机状态期间的阈值电压Vths高于MISFET的有效状态期间的阈值电压Vtha，施加到MISFET的栅极的电压能够采取两个稳定值，并且具有以下关系 满足VDD（1-Vths / VDD）

公开(公告)号：US5933380A

公开(公告)日：1999-08-03

申请号：US871587

申请日：1997-06-09

申请人： Kenji Tsuchida ,  Yukihito Oowaki ,  Kazunori Ohuchi

发明人： Kenji Tsuchida ,  Yukihito Oowaki ,  Kazunori Ohuchi

IPC分类号： H01L21/8242 ,  G11C7/18 ,  G11C11/401 ,  H01L27/108 ,  G11C7/02

CPC分类号： G11C7/18

摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells, the memory cell array being divided into a plurality of blocks, a plurality first bitlines arranged in each of the blocks, the plurality of first bitlines forming a plurality of first bitline pair each having a folded bitline structure with two of the plurality of first bitlines as a basic unit, a plurality second bitlines arranged to correspond to at least one of the blocks and formed above the first bitlines, the plurality of second bitlines forming a plurality of second bitline pair each having a folded bitline structure with two of the plurality of second bitlines as a basic unit, a plurality of sense amplifier circuits, arranged to correspond to the plurality of second bitline pairs, for detecting and amplifying information stored in the memory cells, and a plurality of select circuits for selecting one of two of first bitlines included in one of the plurality of first bitline pairs to selectively connect a selected first bitline with one of two of second bitlines included in one of the plurality of second bitline pairs.

摘要翻译： 半导体存储器件包括具有多个存储单元的存储单元阵列，该存储单元阵列被划分为多个块，多个第一位线布置在每个块中，多个第一位线形成多个第一位线 所述多个第二位线具有折叠的位线结构，其中所述多个第一位线中的两个作为基本单元，多个第二位线被布置成对应于所述块中的至少一个并且形成在所述第一位线上方，所述多个第二位线形成多个 第二位线对，其具有折叠的位线结构，其中所述多个第二位线中的两个作为基本单元;多个读出放大器电路，被布置为对应于所述多个第二位线对，用于检测和放大存储在所述存储器单元中的信息 以及多个选择电路，用于选择包括在所述多个第一位线对之一中的两个第一位线之一至s 选择性地将所选择的第一位线与包括在所述多个第二位线对之一中的第二位线之一中的一个位线连接。

公开(公告)号：US5654912A

公开(公告)日：1997-08-05

申请号：US568500

申请日：1995-12-07

申请人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Hitoshi Kuyama

发明人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Hitoshi Kuyama

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/24

CPC分类号： G11C11/4096 ,  G11C11/4045 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/103

摘要： A semiconductor memory device comprises a memory array in which word lines are driven by a single decoder or a plurality of memory arrays driven by a plurality of decoders operating with the same row address, in the memory array or memory arrays memory cell units in which a plurality of memory cells are connected in series being arranged in the form of an array, a plurality of sense amplifier arrays constituted by arranging a plurality of sense amplifiers each provided for a pair of bit lines or a plurality of pairs of bit lines to read out data from the memory cells of the memory cell arrays, the sense amplifier arrays being divided into a plurality of blocks, and the blocks corresponding to one memory cell array, a register array having a plurality of registers for storing data read out by the plurality of sense amplifiers, the register array being divided into a plurality of blocks, and the blocks corresponding to the sense amplifier block and one memory cell array, and a control circuit for independently controlling the blocks of the sense amplifier arrays and the register array and independently reading out data from the registers in the blocks.

摘要翻译： 半导体存储器件包括存储器阵列，其中字线由单个解码器驱动，或者由存储器阵列或存储器阵列存储单元单元中的由相同行地址操作的多个解码器驱动的多个存储器阵列驱动，其中， 多个存储单元以阵列的形式串联连接，多个读出放大器阵列通过布置多个读出放大器而构成，每个读出放大器分别设置用于一对位线或多对位线以读出 来自存储单元阵列的存储单元的数据，读出放大器阵列被划分为多个块，以及对应于一个存储单元阵列的块，具有多个寄存器的寄存器阵列，用于存储由多个块读出的数据 读出放大器，寄存器阵列被分成多个块，以及对应于读出放大器块和一个存储单元阵列的块，以及控制ci 用于独立控制读出放大器阵列和寄存器阵列的块，并独立地从块中的寄存器读出数据。

公开(公告)号：US07487370B2

公开(公告)日：2009-02-03

申请号：US11216018

申请日：2005-09-01

申请人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

发明人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

IPC分类号： G06F1/00

CPC分类号： G06F1/26 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

摘要： According to the present invention, there is provided a semiconductor device including a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level. The power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号 电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平。 电源电路基于施加到其上的第二控制信号输出具有第二电平的内部电源电压。

公开(公告)号：US06906944B2

公开(公告)日：2005-06-14

申请号：US10676004

申请日：2003-10-02

申请人： Yoshiaki Takeuchi ,  Yukihito Oowaki

发明人： Yoshiaki Takeuchi ,  Yukihito Oowaki

IPC分类号： G11C14/00 ,  G11C11/22

CPC分类号： G11C11/22

摘要： A ferroelectric memory has a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks, a boost power circuit provided in each block of the memory cell array to generate a boost voltage required for operation of the memory, a boost power switch provided between a power line connected to an external power terminal and a power supply terminal of each boost power circuit, and remaining ON during normal operation of the memory, a voltage detector circuit for detecting a drop of voltage level of the power line, and a switch control circuit for turning off the boost power switches in the blocks of the memory cell array excluding the boost power switch in a currently selected block in response to the voltage detector circuit.

摘要翻译： 铁电存储器具有具有铁电电容器的存储单元阵列，其被分成多个块，设置在存储单元阵列的每个块中的升压功率电路，以产生存储器的操作所需的升压电压， 升压电源开关，其设置在连接到外部电源端子的电力线与每个升压电力电路的电源端子之间，并且在正常操作期间保持ON;电压检测器电路，用于检测电力线的电压水平的下降 以及开关控制电路，用于响应于电压检测器电路，关闭当前选择的块中除了升压功率开关之外的存储单元阵列的块中的升压功率开关。

公开(公告)号：US06611450B2

公开(公告)日：2003-08-26

申请号：US10087837

申请日：2002-03-05

申请人： Yukihito Oowaki ,  Sumiko Doumae

发明人： Yukihito Oowaki ,  Sumiko Doumae

IPC分类号： G11C700

CPC分类号： G11C11/22

摘要： A ferroelectric random access memory is disclosed, which comprises a cell array including a plurality of memory cells each having a ferroelectric memory device and a cell selecting transistor connected in series to the ferroelectric storage device, and imprint restricting circuit configured to restrict generation of an imprint by setting a polarization amount of a ferroelectric film of the ferroelectric memory device in the memory cell to an amount smaller than a polarization amount generated at a normal write time.