公开(公告)号：US5951704A

公开(公告)日：1999-09-14

申请号：US802857

申请日：1997-02-19

Applicant: Robert F. Sauer ,  Kiyoshi Fukushima ,  Hiroaki Yamoto

Inventor： Robert F. Sauer ,  Kiyoshi Fukushima ,  Hiroaki Yamoto

IPC: G06F11/22 ,  G01R31/319 ,  G06F11/26 ,  G06F9/455

CPC classification number: G06F11/261 ,  G01R31/31917

Abstract: An emulator software in a semiconductor test system for emulating hardware in the semiconductor test system as well as a semiconductor device to be tested without need to use an actual test system hardware. The emulator software includes an emulator unit which emulates a function of each hardware unit of the test system, a device emulator which emulates a function of a semiconductor device to be tested, a data collecting part for acquiring data from the emulator unit necessary for carrying out a test program, and a device test emulator which generates a test signal to be applied to the device emulator based on the acquired data and compares the resultant signal from the device emulator with the expected data and stores the comparison result therein. In the other aspect, the emulator is combined with the operating system of the semiconductor test system which is capable of easily modifying the software when there is a change or replacement of the hardware of the test system so that the transmission of the control data for the hardware and its operation or the development of the test program can be carried out without using the hardware of the test system.

Abstract translation: 用于模拟半导体测试系统中的硬件的半导体测试系统中的仿真器软件以及要测试的半导体器件，而不需要使用实际的测试系统硬件。 仿真器软件包括仿真测试系统的每个硬件单元的功能的仿真器单元，模拟要测试的半导体器件的功能的器件仿真器，用于从执行所需的仿真器单元获取数据的数据收集部件 测试程序和设备测试仿真器，其基于所获取的数据生成要应用于设备仿真器的测试信号，并将来自设备仿真器的结果信号与预期数据进行比较并将比较结果存储在其中。 另一方面，仿真器与半导体测试系统的操作系统组合，当测试系统的硬件发生变化或更换时，能够容易地修改软件，以便传输控制数据 可以在不使用测试系统的硬件的情况下执行硬件及其操作或开发测试程序。

公开(公告)号：US5914964A

公开(公告)日：1999-06-22

申请号：US765048

申请日：1997-05-09

Applicant: Takashi Saito ,  Hiromi Oshima

Inventor： Takashi Saito ,  Hiromi Oshima

IPC: G01R31/28 ,  G01R31/3193 ,  G11C29/00 ,  G11C29/44 ,  G11C29/56 ,  G06F11/00

CPC classification number: G11C29/56 ,  G11C29/44 ,  G01R31/31935

Abstract: A memory fail analysis device for a semiconductor test system is attained in which fail data of a plurality of bits is read out in parallel to count the overall fail bits in a short period of time. In a fail bit counting device in a fail memory for the semiconductor memory test system, a fail memory block 358 is provided which is recognized as a single memory when measuring the MUT while divided into M blocks to read the stored data in M bits parallel at the same time when counting the number of fail bits. Further, a fail counter 360 is provided which receives the M bit data and encodes the number of either high or low logic levels in the data into binary code data and counts the binary code data to accumulate the counted number.

Abstract translation: PCT No.PCT / JP96 / 02016 Sec。 371日期1997年5月9日 102（e）日期1997年5月9日PCT提交1996年7月19日PCT公布。 出版物WO97 / 04328 日期1997年2月6日获得半导体测试系统的存储器故障分析装置，其中并行读出多个位的故障数据以在短时间内对整个故障位进行计数。 在用于半导体存储器测试系统的故障存储器中的故障比特计数装置中，提供了一个故障存储器块358，其在测量MUT时被识别为单个存储器，同时被分成M个块，以M位并行地读取存储的数据 同时计数故障位数。 此外，提供了一个接收M位数据并将数据中的高或低逻辑电平的数目编码成二进制码数据并对二进制码数据进行计数以累计计数的故障计数器360。

公开(公告)号：US5867030A

公开(公告)日：1999-02-02

申请号：US504455

申请日：1995-07-20

Applicant: Kazuhiko Sato

Inventor： Kazuhiko Sato

IPC: G01R27/28 ,  G01R31/26 ,  G01R31/319

CPC classification number: G01R31/31937 ,  G01R31/2882 ,  G01R31/31725

Abstract: The present invention provides a simple circuit for measuring the delay time between a driver (DR) and a device under test (DUT), and the (DUT) and a comparator (CP) during the connection state of an I/O test where separate driver and comparator paths are used. In the connection circuit of the I/O test using two I/O common pins to connect to one of the pins of the DUT, a terminal pin of a DUT socket corresponding to the DUT pin is grounded. Furthermore, in the connection circuit of the I/O test using a DR-only pin and an I/O common pin to connect to the DUT pin, the terminal pin of the DUT socket is grounded and a standard comparator is employed.

Abstract translation: 本发明提供一种用于在I / O测试的连接状态期间测量驱动器（DR）和被测器件（DUT）之间的延迟时间以及（DUT）和比较器（CP）的简单电路，其中分离 使用驱动器和比较器路径。 在使用两个I / O公共引脚连接到DUT的一个引脚的I / O测试的连接电路中，与DUT引脚相对应的DUT插座的端子引脚接地。 此外，在使用仅DR引脚和I / O公共引脚连接到DUT引脚的I / O测试的连接电路中，DUT插座的端子引脚接地，并使用标准比较器。

公开(公告)号：US5865319A

公开(公告)日：1999-02-02

申请号：US671331

申请日：1996-06-27

Applicant: Hiroshi Okuda ,  Shin Nemoto ,  Hisao Hayama ,  Katsumi Kojima

Inventor： Hiroshi Okuda ,  Shin Nemoto ,  Hisao Hayama ,  Katsumi Kojima

IPC: G01R31/01 ,  G01R31/28 ,  B07C5/344

CPC classification number: G01R31/2893 ,  G01R31/01 ,  G01R31/2851

Abstract: An automatic test handler system for automatically supplying IC devices to be tested to an IC tester and sorting the tested IC devices based on the test results. The system includes a testing machine for testing the IC devices by contacting the IC devices with test contactors. Test signals are provided from the IC tester and the resulting signals from the IC devices are received. The testing machine is installed in a test room in which dust, temperature and humidity are controlled in a high degree. A sorting machine is installed outside of the test room for sorting the IC devices that have been tested based on the test results. The sorting machine has a plurality of sort stations for receiving the IC devices based on categories defined in the test results. Tray cassettes hold a plurality of IC trays containing the IC devices, and both the tray cassettes and IC trays are provided with identification numbers. The trays are horizontally transferred on the testing machine and the sorting machine, and a data communication network connected between the testing machine and the sorting machine transmits the test results and position information of the IC devices in the IC trays.

Abstract translation: 一种自动测试处理系统，用于根据测试结果自动向IC测试人员提供要测试的IC器件并对测试的IC器件进行排序。 该系统包括用于通过将IC器件与测试接触器接触来测试IC器件的测试机。 从IC测试器提供测试信号，并接收来自IC器件的结果信号。 试验机安装在高度控制灰尘，温度和湿度的试验室内。 分拣机安装在测试室外，用于根据测试结果对已经测试的IC器件进行分类。 分选机具有多个分类站，用于基于测试结果中定义的类别接收IC设备。 托盘盒保持包含IC器件的多个IC托盘，托盘盒和IC托盘都具有标识号。 托盘在测试机和分选机上水平传送，连接在测试机与分选机之间的数据通信网络将IC设备的测试结果和位置信息发送到IC托盘。

公开(公告)号：US5847559A

公开(公告)日：1998-12-08

申请号：US704622

申请日：1996-12-23

Applicant: Hiroaki Takaoku ,  Takayoshi Fukui

Inventor： Hiroaki Takaoku ,  Takayoshi Fukui

IPC: G01R23/173 ,  H03L7/18 ,  G01R27/26

CPC classification number: H03L7/1806 ,  G01R23/173

Abstract: An improved local oscillator for use in a digital step sweep is capable of minimizing dynamic spurious which is an inverse of the unit step time T.sub.step. The local oscillator includes a random clock delay 12 which provides a random clock 12.sub.rndclk to the DDS 40 to modify a time length of the unit step time T.sub.step for sweeping the local oscillator to be random.

Abstract translation: PCT No.PCT / JP96 / 00115 Sec。 371日期：1996年12月23日 102（e）日期1996年12月23日PCT提交1996年1月23日PCT公布。 公开号WO96 / 23231 日期1996年8月1日用于数字步进扫描的改进的本地振荡器能够最小化动态寄生，这是单位步进时间Tstep的倒数。 本地振荡器包括随机时钟延迟12，其向DDS 40提供随机时钟12rndclk，以修改用于将本地振荡器扫描为随机的单位步进时间Tstep的时间长度。

公开(公告)号：US5835969A

公开(公告)日：1998-11-10

申请号：US517271

申请日：1995-08-22

Applicant: Toru Inagaki ,  Kenichi Fujisaki

Inventor： Toru Inagaki ,  Kenichi Fujisaki

IPC: G01R31/3183 ,  G01R31/3181 ,  G01R31/319 ,  G06F9/34 ,  G06F12/00 ,  G06F12/02 ,  G11C29/04 ,  G11C29/10 ,  G11C29/18 ,  G11C29/20 ,  G06F9/26 ,  G06F12/10

CPC classification number: G06F9/34 ,  G01R31/31813 ,  G11C29/18 ,  G11C29/20 ,  G01R31/31921

Abstract: An address pattern generator for testing a semiconductor device, particularly, a synchronous DRAM is disclosed. The address pattern generator can switch an interleave mode and a sequential mode of address generation for a semiconductor device under test during a test process in real time and generates column addresses for the device under test by a Y address generation section alone. The address generator includes an address selector that selects and outputs from a lower Y address signal, Z address signal, and an operation mode control signal is arranged, a conversion memory that outputs certain conversion table contents is arranged, a multiplexer that selects and outputs an output from the conversion memory and the lower Y address signal in accordance with the burst length control signal. In another aspect, the address pattern generator includes a counter that loads the lower address signal from the Y address generator section for the sequential mode and loads a fixed value for the interleave mode, an exclusive OR gate that provides an output signal of the counter to an input terminal and the lower address signal from the Y address generation section to the other input terminal, and a multiplexer that selects the output signal of the counter for the sequential mode and the output signal of the exclusive OR gate for the interleave mode.

Abstract translation: 公开了一种用于测试半导体器件，特别是同步DRAM的地址模式发生器。 地址模式发生器可以在测试过程中实时地切换待测半导体器件的交错模式和顺序模式的地址生成，并且由Y地址生成部分单独生成被测器件的列地址。 地址生成器包括：地址选择器，其从较低的Y地址信号Z地址信号中选择和输出，并且布置有操作模式控制信号;布置输出特定转换表内容的转换存储器;选择并输出 根据突发长度控制信号从转换存储器输出下Y位地址信号。 在另一方面，地址模式发生器包括一个计数器，用于为顺序模式加载来自Y地址生成器部分的较低地址信号，并为交错模式加载固定值，异或门将计数器的输出信号提供给 输入端子和从Y地址产生部分到另一个输入端子的低地址信号，以及多路复用器，用于选择顺序模式的计数器的输出信号和用于交织模式的异或门的输出信号。

公开(公告)号：US5825191A

公开(公告)日：1998-10-20

申请号：US617316

申请日：1996-03-18

Applicant: Hironobu Niijima ,  Hiroaki Kobayashi

Inventor： Hironobu Niijima ,  Hiroaki Kobayashi

IPC: G01R31/302 ,  G01R31/307 ,  H01L21/66 ,  G01R31/305 ,  G01R31/28

CPC classification number: G01R31/307

Abstract: The present invention is to provide an IC fault location tracing apparatus with which a user having any knowledge of the DUT design is easily able to identify the IC fault location in a short period of time. The IC fault location tracing apparatus of the present invention includes a control device instructing visual field data to the charged particle ray tester and capturing different images of said electric potential contrast images from the charged particle ray tester, wherein said control device further includes: a fault-suspected layout pattern/net recognition means; a n output gate recognition means for fault-suspected layout patterns; an input net polygon recognition means corresponding to input net of the output gate of the fault-suspected layout pattern; a visual field determination means determining next visual field data for tracing fault location; a layout (visual field) display means instructing next layout (visual field) data to the charged particle ray tester; a memory device storing net layout corresponding information and device-layout corresponding information.

Abstract translation: 本发明提供一种IC故障定位跟踪装置，具有DUT设计知识的用户能够在短时间内容易地识别IC故障位置。 本发明的IC故障位置跟踪装置包括控制装置，指示带电粒子射线检测器的视场数据，并从所述带电粒子射线检测器捕获所述电位对比图像的不同图像，其中所述控制装置还包括：故障 - 预期布局模式/净识别手段; 用于故障怀疑布局图案的n个输出门识别装置; 输入网络多边形识别装置，对应于故障怀疑布局图案的输出门的输入网; 视场确定装置确定跟踪故障位置的下一个视野数据; 布局（视野）显示装置指示向带电粒子射线测试仪的下一个布局（视野）数据; 存储设备对应信息和设备布局对应信息的存储设备。

公开(公告)号：US5818219A

公开(公告)日：1998-10-06

申请号：US562006

申请日：1995-11-22

Applicant: Hiroyuki Hama ,  Kazunari Suga

Inventor： Hiroyuki Hama ,  Kazunari Suga

IPC: G01R31/28 ,  G01R31/02

CPC classification number: G01R31/2887

Abstract: A semiconductor test system having a test head connection apparatus for connecting and disconnecting a test head of the test system with a wafer prober or a test handler includes a housing formed outside of the semiconductor test system wherein the housing is integral with a body of the test system, a pair of arms provide on the housing for holding the test head wherein the test head rotates about 180 degrees in the arms so that a performance board on the test head faces with a corresponding member on the wafer prober or the test handler, at least one rail built on a floor in a direction which accurately positioning the test head right over the wafer prober or the test handler, a guide mechanism provided on the housing to guide an up-down movement of the arms, a plurality of free casters provided at the bottom of the housing to transfer the test system and the test head toward the wafer prober or the test handler along the rail, and a balancing mechanism for offsetting the weight of the test head so that the up-down movement of the arms holding the test head is controlled with substantially less power.

Abstract translation: 具有测试头连接装置的半导体测试系统，用于使用晶片探测器或测试处理器连接和断开测试系统的测试头，该壳体形成在半导体测试系统外部，其中壳体与测试体一体 系统中，一对臂提供在壳体上用于保持测试头，其中测试头在臂中旋转约180度，使得测试头上的性能板与晶片探测器或测试处理器上的对应构件相对， 至少一个轨道，其沿着将测试头准确地定位在晶片探测器或测试处理器上方向的地板上，引导机构设置在壳体上以引导臂的上下运动，提供多个自由脚轮 在壳体的底部，沿着轨道将测试系统和测试头转移到晶片探测器或测试处理器，以及用于抵消th的重量的平衡机构 e测试头，使得保持测试头的臂的上下移动以显着更小的功率被控制。

公开(公告)号：US5796753A

公开(公告)日：1998-08-18

申请号：US700451

申请日：1996-11-18

Applicant: Yoshiaki Kato

Inventor： Yoshiaki Kato

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/319 ,  G06F11/22 ,  G06F11/00

CPC classification number: G01R31/31908 ,  G01R31/2834 ,  G01R31/31724

Abstract: A test pattern transfer apparatus is to improve overall throughput of a semiconductor test system which has an engineering work station for functioning as a host computer, a test controller for controlling an operation of the semiconductor test system and a pattern memory for generating test patterns transferred from a hard disk of the engineering work station. The test pattern transfer apparatus simplifies the pathways for transferring the test patterns so as to reduce the time required for the pattern transfer by directly transferring the test pattern from the work station to the pattern memory without passing through the test controller. The test pattern transfer apparatus includes an interface controller whereby the test pattern from the engineering work station is either directly transferred to the pattern memory or indirectly transferred to the pattern memory through the test controller.

Abstract translation: PCT No.PCT / JP95 / 02692 Sec。 371日期：1996年11月18日 102（e）1996年11月18日日期PCT 1995年12月26日PCT PCT。 公开号WO96 / 20409 日期1996年7月4日测试图案转移装置是提高具有用作主计算机的工程工作站的半导体测试系统的总体吞吐量，用于控制半导体测试系统的操作的测试控制器和用于 生成从工程工作站的硬盘传输的测试模式。 测试图形传送装置简化了用于传送测试图案的路径，以便通过将测试图案从工作站直接传送到图案存储器而不通过测试控制器来减少图案转移所需的时间。 测试图形传送装置包括接口控制器，其中来自工程工作站的测试图案被直接传送到图案存储器，或者通过测试控制器间接传送到图案存储器。

公开(公告)号：US5764048A

公开(公告)日：1998-06-09

申请号：US637053

申请日：1996-04-24

Applicant: Haruo Yoshida

Inventor： Haruo Yoshida

IPC: G01R1/28 ,  G01R19/00 ,  G01R19/18 ,  G01R17/06

CPC classification number: G01R1/28 ,  G01R19/0084

Abstract: An ultra high accuracy voltage measurement system utilizes a Josephson junction voltage generator whose voltage is controlled by a high precision frequency. The voltage measurement system to measure an input DC voltage incudes: a microwave oscillator which generates a microwave signal whose frequency is variable by a voltage applied thereto; an atomic frequency standard which generates a standard frequency signal with extremely high accuracy and stability; a frequency synthesizer which synthesizes a frequency signal based on the atomic frequency standard; a phase lock loop for synchronizing the microwave signal with the frequency signal from the frequency synthesizer; a Josephson junction voltage generator which is soaked with liquid helium and generates a standard voltage determined by the frequency and a power level of the microwave signal; a bias circuit for supplying a bias current to the Josephson junction voltage generator; a switch group for alternately changing polarities of the input voltage and the standard voltage; a difference detector for detecting a voltage difference between the input voltage and the standard voltage; a feedback circuit to control the frequency of the microwave signal through the phase lock loop so that the voltage difference is canceled; and a system controller to control an overall operation of the voltage measurement system.

Abstract translation: 超高精度电压测量系统利用约瑟夫逊结电压发生器，其电压由高精度频率控制。 用于测量输入DC电压的电压测量系统包括：微波振荡器，其产生频率可通过施加于其上的电压而变化的微波信号; 产生具有极高精度和稳定性的标准频率信号的原子频率标准; 频率合成器，其基于原子频率标准合成频率信号; 用于使微波信号与来自频率合成器的频率信号同步的锁相环; 约瑟夫逊结电压发生器，其用液氦浸泡并产生由微波信号的频率和功率电平确定的标准电压; 用于向约瑟夫逊结电压发生器提供偏置电流的偏置电路; 用于交替改变输入电压和标准电压的极性的开关组; 差分检测器，用于检测输入电压和标准电压之间的电压差; 反馈电路，通过锁相环控制微波信号的频率，消除电压差; 以及控制电压测量系统的整体操作的系统控制器。