公开(公告)号：US20150255308A1

公开(公告)日：2015-09-10

申请号：US14314041

申请日：2014-06-25

Applicant: NATIONAL TAIWAN UNIVERSITY

Inventor： CHING-FUH LIN ,  Yu-Wen CHENG ,  Yu-Zhong LIN

IPC: H01L21/324 ,  C25D7/12 ,  H01L21/02

CPC classification number: H01L21/3245 ,  B81C1/00365 ,  B81C2201/0169 ,  C25D9/04 ,  H01L21/0242 ,  H01L21/0254 ,  H01L21/02631 ,  H01L21/02658

Abstract: An embodiment discloses a method for modulating stress of a semiconductor film and comprises the steps of: providing a substrate; forming a semiconductor film on the substrate; performing an annealing treatment to the formed semiconductor film; and determining a residual stress of the semiconductor film at a certain compress strain, a certain tensile strain, or zero by controlling a temperature of the annealing treatment.

Abstract translation: 实施例公开了一种用于调制半导体膜的应力的方法，包括以下步骤：提供衬底; 在基板上形成半导体膜; 对形成的半导体膜进行退火处理; 并且通过控制退火处理的温度来确定在某一压缩应变，一定的拉伸应变或零点处的半导体膜的残余应力。

公开(公告)号：US08658452B2

公开(公告)日：2014-02-25

申请号：US13003328

申请日：2009-07-08

Applicant: Mourad El-Gamal ,  Frederic Nabki ,  Paul-Vahe Cicek

Inventor： Mourad El-Gamal ,  Frederic Nabki ,  Paul-Vahe Cicek

IPC: H01L21/00 ,  H01L27/14

CPC classification number: B81C1/00666 ,  B81B3/0021 ,  B81B7/008 ,  B81B2201/01 ,  B81B2201/0235 ,  B81B2201/0271 ,  B81B2201/03 ,  B81B2207/015 ,  B81B2207/03 ,  B81C1/00063 ,  B81C1/00246 ,  B81C1/00396 ,  B81C1/00587 ,  B81C2201/014 ,  B81C2201/0169 ,  B81C2201/0174 ,  B81C2203/0721 ,  B81C2203/0735

Abstract: A method of providing microelectromechanical structures (MEMS) that are compatible with silicon CMOS electronics is provided. The method providing for processes and manufacturing sequences limiting the maximum exposure of an integrated circuit upon which the MEMS is manufactured to below 350° C., and potentially to below 250° C., thereby allowing direct manufacturing of the MEMS devices onto electronics, such as Si CMOS circuits. The method further providing for the provisioning of MEMS devices with multiple non-conductive structural layers such as silicon carbide separated with small lateral gaps. Such silicon carbide structures offering enhanced material properties, increased environmental and chemical resilience whilst also allowing novel designs to be implemented taking advantage of the non-conductive material of the structural layer. The use of silicon carbide being beneficial within the formation of MEMS elements such as motors, gears, rotors, translation drives, etc where increased hardness reduces wear of such elements during operation.

Abstract translation: 提供了一种提供与硅CMOS电子器件兼容的微机电结构（MEMS）的方法。 该方法提供了将MEMS制造的集成电路的最大曝光限制在低于350℃并可能低于250℃的工艺和制造顺序，从而允许将MEMS器件直接制造到电子器件上，例如 作为Si CMOS电路。 该方法进一步提供具有多个非导电结构层的MEMS器件，例如用小的侧向间隙分离的碳化硅。 这种碳化硅结构提供增强的材料性能，增加环境和化学弹性，同时还允许利用结构层的非导电材料来实现新颖的设计。 在形成MEMS元件（例如马达，齿轮，转子，平移驱动器等）中使用碳化硅是有益的，其中增加的硬度降低了操作期间这些元件的磨损。

公开(公告)号：US20130052421A1

公开(公告)日：2013-02-28

申请号：US13582525

申请日：2011-03-04

Applicant: Ulrich Wiesner ,  Michael Thompson ,  Hitesh Arora

Inventor： Ulrich Wiesner ,  Michael Thompson ,  Hitesh Arora

IPC: C30B25/04 ,  B32B9/04 ,  B32B3/08 ,  C30B23/04 ,  C30B19/00

CPC classification number: B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0169 ,  C30B1/023 ,  C30B29/08 ,  C30B29/605 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02642 ,  H01L21/28518 ,  Y10T428/24372 ,  Y10T428/24413

Abstract: A method for fabricating a nanostructure utilizes a templated monocrystalline substrate. The templated monocrystalline substrate is energetically (i.e., preferably thermally) treated, with an optional precleaning and an optional amorphous material layer located thereupon, to form a template structured monocrystalline substrate that includes the monocrystalline substrate with a plurality of epitaxially aligned contiguous monocrystalline pillars extending therefrom. The monocrystalline substrate and the plurality of epitaxially aligned contiguous monocrystalline pillars may comprise the same or different monocrystalline materials. The method provides the nanostructure where when the monocrystalline substrate and the plurality of epitaxial aligned contiguous monocrystalline pillars comprise different monocrystalline materials having a bulk crystal structure mismatch of up to about 10 percent, lattice mismatch induced crystal structure defects may be avoided interposed between the monocrystalline substrate and the plurality of epitaxially aligned contiguous monocrystalline pillars, which may have an irregular sidewall shape.

Abstract translation: 制造纳米结构的方法使用模板化单晶衬底。 模板化的单晶衬底在能量上（即，优选热处理），具有可选的预清洗和位于其上的任选的非晶材料层，以形成模板结构的单晶衬底，其包括具有从其延伸的多个外延比对的邻接单晶柱的单晶衬底 。 单晶衬底和多个外延排列的邻接单晶柱可以包括相同或不同的单晶材料。 该方法提供纳米结构，其中当单晶衬底和多个外延对准的邻接单晶柱包含具有高达约10％的体晶结构失配的不同单晶材料时，晶格失配诱发的晶体结构缺陷可以避免插入在单晶衬底 以及可能具有不规则侧壁形状的多个外延排列的邻接单晶柱。

公开(公告)号：US20110111545A1

公开(公告)日：2011-05-12

申请号：US13003328

申请日：2009-07-08

Applicant: Mourad El-Gamal

Inventor： Mourad El-Gamal

IPC: H01L21/02

CPC classification number: B81C1/00666 ,  B81B3/0021 ,  B81B7/008 ,  B81B2201/01 ,  B81B2201/0235 ,  B81B2201/0271 ,  B81B2201/03 ,  B81B2207/015 ,  B81B2207/03 ,  B81C1/00063 ,  B81C1/00246 ,  B81C1/00396 ,  B81C1/00587 ,  B81C2201/014 ,  B81C2201/0169 ,  B81C2201/0174 ,  B81C2203/0721 ,  B81C2203/0735

Abstract: A method of providing microelectromechanical structures (MEMS) that are compatible with silicon CMOS electronics is provided. The method providing for processes and manufacturing sequences limiting the maximum exposure of an integrated circuit upon which the MEMS is manufactured to below 350° C., and potentially to below 250° C., thereby allowing direct manufacturing of the MEMS devices onto electronics, such as Si CMOS circuits. The method further providing for the provisioning of MEMS devices with multiple non-conductive structural layers such as silicon carbide separated with small lateral gaps. Such silicon carbide structures offering enhanced material properties, increased environmental and chemical resilience whilst also allowing novel designs to be implemented taking advantage of the non-conductive material of the structural layer. The use of silicon carbide being beneficial within the formation of MEMS elements such as motors, gears, rotors, translation drives, etc where increased hardness reduces wear of such elements during operation.

Abstract translation: 提供了一种提供与硅CMOS电子器件兼容的微机电结构（MEMS）的方法。 该方法提供了将MEMS制造的集成电路的最大曝光限制在低于350℃并可能低于250℃的工艺和制造顺序，从而允许将MEMS器件直接制造到电子器件上，例如 作为Si CMOS电路。 该方法进一步提供具有多个非导电结构层的MEMS器件，例如用小的侧向间隙分离的碳化硅。 这种碳化硅结构提供增强的材料性能，增加环境和化学弹性，同时还允许利用结构层的非导电材料来实现新颖的设计。 在形成MEMS元件（例如马达，齿轮，转子，平移驱动器等）中使用碳化硅是有益的，其中增加的硬度降低了操作期间这些元件的磨损。

公开(公告)号：US20100032812A1

公开(公告)日：2010-02-11

申请号：US11643235

申请日：2006-12-21

Applicant: Sherif Sedky ,  Ann Witvrouw

Inventor： Sherif Sedky ,  Ann Witvrouw

IPC: H01L29/161 ,  H01L21/20

CPC classification number: B81C1/00666 ,  B81C2201/0169

Abstract: A method is provided for controlling the average stress and the strain gradient in structural silicon germanium layers as used in micromachined devices. The method comprises depositing a single silicon germanium layer on a substrate and annealing a predetermined part of the deposited silicon germanium layer. The process parameters of the depositing and/or annealing steps are selected such that a predetermined average stress and a predetermined strain gradient are obtained in the predetermined part of the silicon germanium layer. Preferably a plasma assisted deposition technique is used for depositing the silicon germanium layer, and a pulsed excimer laser is used for local annealing, with a limited thermal penetration depth. Structural silicon germanium layers for surface micromachined structures can be formed at temperatures substantially below 400° C., which offers the possibility of post-processing micromachined structures on top of a substrate comprising electronic circuitry such as CMOS circuitry. Such structural silicon germanium layers may be also be formed at temperatures not exceeding 210° C., which allows the integration of silicon germanium based micromachined structures on substrates such as polymer films.

Abstract translation: 提供了一种用于控制在微加工装置中使用的结构硅锗层中的平均应力和应变梯度的方法。 该方法包括在衬底上沉积单个硅锗层并退火沉积的硅锗层的预定部分。 选择沉积和/或退火步骤的工艺参数，使得在硅锗层的预定部分中获得预定的平均应力和预定的应变梯度。 优选地，等离子体辅助沉积技术用于沉积硅锗层，并且将脉冲准分子激光器用于具有有限的热穿透深度的局部退火。 用于表面微加工结构的结构硅锗层可以在基本上低于400℃的温度下形成，这提供了在包括诸如CMOS电路的电子电路的衬底之上的后处理微机械加工结构的可能性。 这种结构硅锗层也可以在不超过210℃的温度下形成，这允许将硅锗微加工结构集成在诸如聚合物膜的基底上。

公开(公告)号：US20050194662A1

公开(公告)日：2005-09-08

申请号：US11039068

申请日：2005-01-20

Applicant: Gerhard Schmidt ,  Rudolf Zelsacher ,  Michael Bar ,  Wolfgang Werner ,  Bernhard Winkler

Inventor： Gerhard Schmidt ,  Rudolf Zelsacher ,  Michael Bar ,  Wolfgang Werner ,  Bernhard Winkler

IPC: B81B3/00 ,  B81B7/00 ,  B81C1/00 ,  G01C19/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/58 ,  H01L29/84

CPC classification number: H01L23/564 ,  B81B7/0012 ,  B81C2201/0169 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: A semiconductor component (1) includes a substrate, an active area (2), formed in/on the substrate, and a passivation layer (5) which is provided at least above part of the active area (2). The passivation layer (5) at least partially comprises amorphous, hydrogen-doped carbon. The provision of a passivation layer of this type allows the semiconductor component (1) to be effectively protected against environmental influences.

Abstract translation: 半导体部件（1）包括衬底，形成在衬底中或衬底上的有源区（2）以及设置在有源区（2）的至少上方的钝化层（5）。 钝化层（5）至少部分地包括无定形的氢掺杂碳。 提供这种钝化层可以有效地保护半导体部件（1）免受环境影响。

公开(公告)号：US20040157426A1

公开(公告)日：2004-08-12

申请号：US10410158

申请日：2003-04-10

Inventor： Luc Ouellet ,  Robert Antaki

IPC: H01L021/8242

CPC classification number: B81C1/00246 ,  B81C1/00666 ,  B81C2201/0164 ,  B81C2201/0167 ,  B81C2201/0169 ,  B81C2203/0735

Abstract: A micro-electro-mechanical (MEM) device and an electronic device are fabricated on a common substrate by fabricating the electronic device comprising a plurality of electronic components on the common substrate, depositing a thermally stable interconnect layer on the electronic device, encapsulating the interconnected electronic device with a protective layer, forming a sacrificial layer over the protective layer, opening holes in the sacrificial layer and the protective layer to allow the connection of the MEM device to the electronic device, fabricating the MEM device by depositing and patterning at least one layer of amorphous silicon, and removing at least a portion of the sacrificial layer. In this way, the MEM device can be fabricated after the electronic device on the same substrate.

Abstract translation: 通过在公共衬底上制造包括多个电子部件的电子器件，在公共衬底上制造微电子机械（MEM）器件和电子器件，在电子器件上沉积热稳定的互连层，封装互连 具有保护层的电子器件，在保护层上形成牺牲层，牺牲层中的开孔和保护层，以允许MEM器件与电子器件的连接，通过沉积和图案化制造MEM器件至少一个 非晶硅层，并且去除牺牲层的至少一部分。 以这种方式，MEM装置可以在同一基板上的电子装置之后制造。

公开(公告)号：US06406637B1

公开(公告)日：2002-06-18

申请号：US09557155

申请日：2000-04-25

Applicant: Akira Shimokohbe ,  Seiichi Hata

Inventor： Akira Shimokohbe ,  Seiichi Hata

IPC: H01L21302

CPC classification number: B81C1/00666 ,  B81C2201/0169

Abstract: A thin film made of an amorphous material having a supercooled liquid phase region is formed on a substrate. Then, the thin film is processed by wet-etching, etc. to form a thin film-processed body having, for example, a one side-fixed beam like shape. Subsequently, the thin film-processed body is heated to a temperature within the supercooled liquid phase region and held at the temperature for 0.5-5 minutes. Thereafter, the thin film-processed body is cooled down to room temperature. Then, at least a part of the substrate is removed by wet-etching, etc. to form a thin film-planar structure composed of the thin film-processed body having the one side-fixed beam like shape.

Abstract translation: 在基板上形成由具有过冷液相区域的非晶材料制成的薄膜。 然后，通过湿法蚀刻等处理薄膜，以形成具有例如单侧固定光束形状的薄膜加工体。 随后，将薄膜加工体加热到过冷液相区域内的温度，并保持在该温度0.5-5分钟。 然后，将薄膜处理体冷却至室温。 然后，通过湿蚀刻等除去基板的至少一部分，以形成由具有一个侧面固定的梁状的薄膜加工体构成的薄膜平面结构。