公开(公告)号：US20230335173A1

公开(公告)日：2023-10-19

申请号：US18025457

申请日：2021-09-08

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Hitoshi KUNITAKE

IPC分类号： G11C11/22

CPC分类号： G11C11/221 ,  G11C11/2293 ,  G11C11/2273 ,  G11C11/2275

摘要： A semiconductor device with low power consumption that is capable of non-destructive reading is provided. The semiconductor device includes a first transistor, a second transistor, a third transistor, a first FTJ element, and a second FTJ element. A first terminal of the first transistor is electrically connected to an output terminal of the first FTJ element, an input terminal of the second FTJ element, and a gate of the second transistor. A first terminal of the second transistor is electrically connected to a second terminal of the third transistor. For data writing, polarization is caused in each of the first FTJ element and the second FTJ element in accordance with data. For data reading, a voltage that does not cause a change in polarization is applied between the input terminal of the first FTJ element and the output terminal of the second FTJ element, a potential is supplied to the gate of the second transistor, and a current or voltage corresponding to data is obtained from the first terminal of the second transistor.

公开(公告)号：US20230186965A1

公开(公告)日：2023-06-15

申请号：US18084884

申请日：2022-12-20

申请人： Micron Technology, Inc.

发明人： Daniele Vimercati

IPC分类号： G11C11/22

CPC分类号： G11C11/2255 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2293

摘要： Methods, systems, and devices for deck-level shunting in a memory device are described. A memory device may include memory arrays arranged in a stack of decks over a substrate, and a combination of deck selection circuitry and shunting circuitry may be distributed among the decks to leverage common substrate-based circuitry, such as logic or addressing circuitry. For example, each memory array of a stack may include a set of digit lines and deck selection circuitry, such as deck selection transistors or other switching circuitry, operable to couple the set of digit lines with a column decoder that may be shared among multiple decks. Each memory array of a stack also may include shunting circuitry, such as shunting transistors or other switching circuitry operable to couple the set of digit lines with a plate node, thereby equalizing a voltage across the memory cells of the respective memory array.

公开(公告)号：US20180358073A1

公开(公告)日：2018-12-13

申请号：US15619158

申请日：2017-06-09

申请人： Micron Technology, Inc.

发明人： Umberto Di Vincenzo

IPC分类号： G11C11/22

CPC分类号： G11C11/2273 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2293

摘要： Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. The duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

公开(公告)号：US10153021B1

公开(公告)日：2018-12-11

申请号：US15619158

申请日：2017-06-09

申请人： Micron Technology, Inc.

发明人： Umberto Di Vincenzo

IPC分类号： G11C11/22

CPC分类号： G11C11/2273 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2293

摘要： Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. The duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

公开(公告)号：US10153020B1

公开(公告)日：2018-12-11

申请号：US15618393

申请日：2017-06-09

申请人： Micron Technology, Inc.

发明人： Daniele Vimercati

IPC分类号： G11C11/22

CPC分类号： G11C11/2273 ,  G11C11/2275 ,  G11C11/2293

摘要： Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated in volatile and non-volatile modes. For example, a memory cell may operate in a non-volatile mode and then operate in a volatile mode following a command initiated by a controller while the cell is operating in the non-volatile mode. The memory cell may operate in the volatile mode and then operate in the non-volatile mode following a subsequent command. In some examples, one memory cell of the memory array may operate in the non-volatile mode while another memory cell of the memory array operates in the volatile mode.

公开(公告)号：US10083731B2

公开(公告)日：2018-09-25

申请号：US15067954

申请日：2016-03-11

申请人： Micron Technology, Inc.

发明人： Daniele Vimercati

IPC分类号： G11C11/22

CPC分类号： G11C11/2273 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2293

摘要： Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be selected using a selection component that is in electronic communication with a sense amplifier and a ferroelectric capacitor of a ferroelectric memory cell. A voltage applied to the ferroelectric capacitor may be sized to increase the signal sensed during a read operation. The ferroelectric capacitor may be isolated from the sense amplifier during the read operation. This isolation may avoid stressing the ferroelectric capacitor which may otherwise occur due to the applied read voltage and voltage introduce by the sense amplifier during the read operation.

公开(公告)号：US10064014B2

公开(公告)日：2018-08-28

申请号：US15713309

申请日：2017-09-22

申请人： Ivani, LLC

发明人： John Wootton ,  Matthew Wootton ,  Chris Nissman ,  Victoria Preston ,  Jonathan Clark ,  Justin McKinney ,  Claire Barnes ,  Zhecan Wang ,  Xinyu Xiao

IPC分类号： G08B23/00 ,  H04W4/02 ,  H04L5/00 ,  H04L1/00 ,  H04W64/00 ,  G01V3/12 ,  H04W4/04 ,  H04B17/318 ,  H04W4/80 ,  H04B17/27 ,  G11C11/22 ,  G01V1/00

CPC分类号： H04W4/023 ,  G01V1/001 ,  G01V3/12 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2293 ,  G11C11/2297 ,  H04B17/27 ,  H04B17/318 ,  H04L1/0018 ,  H04L5/006 ,  H04W4/30 ,  H04W4/33 ,  H04W4/80 ,  H04W64/00

摘要： Systems and methods for detecting the presence of a body in a network without fiducial elements, using signal absorption, and signal forward and reflected backscatter of radio frequency (RF) waves caused by the presence of a biological mass in a communications network.

公开(公告)号：US20180174636A1

公开(公告)日：2018-06-21

申请号：US15787101

申请日：2017-10-18

申请人： SEONG-HWAN JEON ,  KYUNG-SOO HA ,  JIN-SEOK HEO ,  IN-DAL SONG ,  JUNG-HWAN CHOI

发明人： SEONG-HWAN JEON ,  KYUNG-SOO HA ,  JIN-SEOK HEO ,  IN-DAL SONG ,  JUNG-HWAN CHOI

IPC分类号： G11C11/402 ,  G11C11/22 ,  G11C7/22

CPC分类号： G11C11/4023 ,  G11C7/1012 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/2293 ,  G11C11/4093

摘要： A data alignment circuit of a semiconductor memory device including: a data sampling circuit configured to receive a data sequence and an internal data strobe signal, wherein the data sampling circuit samples the data sequence based on the internal data strobe signal to generate first and second data sequences; a division circuit configured to receive a clock signal and the internal data strobe signal, divide the clock signal to produce a divided clock signal and output an alignment control signal by sampling the divided clock signal based on the internal data strobe signal; and a data alignment block configured to receive the first and second data sequences, and the alignment control signal, and align the first and second data sequences in parallel to output internal data.

公开(公告)号：US20180102157A1

公开(公告)日：2018-04-12

申请号：US15291711

申请日：2016-10-12

申请人： Micron Technology, Inc.

发明人： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC分类号： G11C11/22

CPC分类号： G11C11/2259 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2277 ,  G11C11/2293

摘要： Methods, systems, and devices are described for operating a memory array. A first voltage may be applied to a memory cell to activate a selection component of the memory cell prior to applying a second voltage to the memory cell. The second voltage may be applied to facilitate a sensing operation once the selection component is activated. The first voltage may be applied during a first portion of an access operation and may be used in determining a threshold voltage of the selection component. The subsequently applied second voltage may be applied during a second portion of the access operation and may have a magnitude associated with a preferred voltage for accessing a ferroelectric capacitor of the memory cell. In some cases, the second voltage has a greater rate of increase over time (e.g., a greater “ramp”) than the first voltage.

公开(公告)号：US09934837B2

公开(公告)日：2018-04-03

申请号：US15057914

申请日：2016-03-01

申请人： Micron Technology, Inc.

发明人： Daniele Vimercati ,  Scott James Derner ,  Umberto Di Vincenzo ,  Christopher John Kawamura ,  Eric S. Carman

IPC分类号： G11C11/22

CPC分类号： G11C11/2273 ,  G11C11/221 ,  G11C11/2293

摘要： Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.