Method and system for detecting fault attacks

    公开(公告)号:US09929858B2

    公开(公告)日:2018-03-27

    申请号:US14860619

    申请日:2015-09-21

    申请人: NXP B.V.

    发明人: Sebastien Riou

    摘要: In an embodiment, an integrated circuit (IC) device for detecting fault attacks is disclosed. In the embodiment, the IC device includes a main CPU core, memory coupled to the main CPU core, and a co-processor core including a checksum generation module, the co-processor core coupled to the main CPU core, wherein the main CPU core is configured to direct the co-processor core to process data from the memory and the co-processor core is configured to process the data, in part, by feeding internal signals to the checksum generation module and wherein the co-processor core is further configured to return a checksum value generated by the checksum generation module to the main CPU core.

    HYBRID AES-SMS4 HARDWARE ACCELERATOR
    48.
    发明申请

    公开(公告)号:US20180062829A1

    公开(公告)日:2018-03-01

    申请号:US15252741

    申请日:2016-08-31

    申请人: Intel Corporation

    IPC分类号: H04L9/06

    摘要: A hybrid AES-SMS4 hardware accelerator is described. A System on Chip implementing a hybrid AES-SMS4 hardware accelerator may include a processor core and a single hardware accelerator coupled to the processor core, the single hardware accelerator to encrypt or decrypt data. The single hardware accelerator may include a first block cipher to encrypt or decrypt the data according to a first encryption algorithm and a second block cipher to encrypt or decrypt the data according to a second encryption algorithm. The accelerator may further include a combined substitution box (Sbox) coupled to the first block cipher and the second block cipher, the combined Sbox comprising logic to perform Galois Field (GF) multiplications and inverse computations, wherein the inverse computations are common to the first block cipher and the second block cipher.