公开(公告)号：US20140192938A1

公开(公告)日：2014-07-10

申请号：US14066774

申请日：2013-10-30

Applicant: FUJITSU LIMITED

Inventor： Hirotaka TAMURA

IPC: H04L7/00

CPC classification number: H04L7/0041 ,  H03K5/00 ,  H03K2005/00104 ,  H03M1/1215 ,  H03M9/00

Abstract: A signal processing circuit includes: a delay line configured to output, to a plurality of taps, signals with different delay times obtained by delaying an input signal, respectively; and a plurality of synchronization circuits configured to sample the signals from the plurality of taps in a phase in synchronization with a clock signal, wherein each of the plurality of synchronization circuits samples a sample signal from one of the plurality of taps in different phases and outputs a plurality of output signals.

Abstract translation: 信号处理电路包括：延迟线，被配置为向多个抽头输出分别通过延迟输入信号而获得的不同延迟时间的信号; 以及多个同步电路，其被配置为与时钟信号同步地从所述多个抽头中抽取所述信号，其中所述多个同步电路中的每一个从不同相位的多个抽头中的一个抽头采样信号 多个输出信号。

公开(公告)号：US20140185658A1

公开(公告)日：2014-07-03

申请号：US13729405

申请日：2012-12-28

Applicant: LSI CORPORATION

Inventor： Vladimir Sindalovsky ,  Lane A. Smith ,  Mohammad S. Mobin

IPC: H04B1/40

CPC classification number: H04B1/40 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/0058 ,  H04L7/0337

Abstract: A SerDes data sampling controller that includes a gear shifting data sampling clock that zeroes the data sampling skew at the center of the unit interval during the CDR phase lock stage, and then skews the data sample timing away from the center of the unit interval as the DFE coefficients adapt during the data transfer stage. This allows the controller to implement the best (unskewed) data sample timing during the CDR phase locking stage, and then skew the data sample timing after the DFE coefficients have adapted to provide the best (skewed) data sample timing for data bit sampling during the data transfer stage. The data sampling gear shifter may apply a variable skew value to the transition sampling or quadrature (Q) data sampling clock differentially varying the quadrature (Q) transition sampling clock from the inphase (I) data sampling clock.

Abstract translation: 一个SerDes数据采样控制器，其包括一个换档数据采样时钟，该数据采样时钟在CDR相位锁定阶段期间将单位间隔中心处的数据采样偏差置零，然后将数据采样定时从该单位间隔的中心偏离为 DFE系数在数据传输阶段适应。 这允许控制器在CDR相位锁定阶段期间实现最佳（非限制）数据采样定时，然后在DFE系数适应于在期间为数据位采样提供最佳（偏斜））数据采样定时之前扭曲数据采样定时 数据传输阶段。 数据采样齿轮换档器可以向从同相（I）数据采样时钟差分改变正交（Q）转换采样时钟的转换采样或正交（Q）数据采样时钟施加可变偏移值。

公开(公告)号：US08710882B2

公开(公告)日：2014-04-29

申请号：US13607490

申请日：2012-09-07

Applicant: Bin Zhang

Inventor： Bin Zhang

IPC: H03L7/06 ,  H03L7/089

CPC classification number: H03L7/0891 ,  H03L7/0814 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/0337

Abstract: A calibration device and related method for a phase difference between data signal and clock signal are disclosed. An apparatus of the invention includes: an adjustable delay circuit for delaying at least one of a first input signal and a second input signal according to a delay control signal, and generating a first signal and a second signal; a phase detection circuit for detecting a phase difference between the first signal and the second signal to output a phase difference signal; a charge pump and a capacitor for outputting a control signal according to the phase difference signal; a comparison circuit for outputting a comparison result according to the control signal; and, a digital control circuit for outputting the delay control signal according to the comparison result.

Abstract translation: 公开了一种用于数据信号和时钟信号之间的相位差的校准装置及相关方法。 本发明的装置包括：可调节延迟电路，用于根据延迟控制信号延迟第一输入信号和第二输入信号中的至少一个，并产生第一信号和第二信号; 相位检测电路，用于检测第一信号和第二信号之间的相位差，以输出相位差信号; 电荷泵和电容器，用于根据相位差信号输出控制信号; 比较电路，用于根据控制信号输出比较结果; 以及数字控制电路，用于根据比较结果输出延迟控制信号。

公开(公告)号：US20130294597A1

公开(公告)日：2013-11-07

申请号：US13875447

申请日：2013-05-02

Applicant: FUTUREWEI TECHNOLOGIES, INC.

Inventor： Cao Shi ,  Amir H. Fazlollahi ,  Jianhua Liu

IPC: H04L7/00

CPC classification number: H04L7/0041 ,  H04B3/32 ,  H04J3/0682 ,  H04L5/14 ,  H04L5/1469 ,  H04L25/14 ,  H04L27/2646 ,  H04L27/2662 ,  H04M11/062

Abstract: A method comprising transmitting a delay value to each of a plurality of digital subscriber line (DSL) transceivers, by a distribution point unit (DPU), and receiving a plurality of signals at substantially the same time, wherein each of the plurality of signals is from a different DSL transceiver in the plurality of DSL transceivers and transmitted at different times based on the delay value and a corresponding propagation delay.

Abstract translation: 一种方法，包括通过分发点单元（DPU）向多个数字用户线（DSL）收发机中的每一个发送延迟值，并且在基本上相同的时间接收多个信号，其中所述多个信号中的每一个是 来自多个DSL收发器中的不同DSL收发器，并且基于延迟值和相应的传播延迟在不同时间发送。

公开(公告)号：US20130142243A1

公开(公告)日：2013-06-06

申请号：US13816770

申请日：2012-06-13

Applicant: Yuki Minoda ,  Eiichi Muramoto

Inventor： Yuki Minoda ,  Eiichi Muramoto

IPC: H04L7/00

CPC classification number: H04L7/0041 ,  H04L47/25 ,  H04L47/283 ,  H04N21/2402 ,  H04N21/26216 ,  H04N21/6373

Abstract: A transmitting device can suppress degradation of the video quality and determine a proper transmission rate, and include a transmitting unit that transmits a communication packet to a receiving device, a receiving unit that receives a feedback packet, which is a response signal corresponding to the communication packet, from the receiving device, a detecting unit that detects a change of a reception interval of the feedback packet, and a transmission rate determining unit that decreases a transmission rate at which the transmitting unit transmits the communication packet in the case where the change of the reception interval is detected, and increases the transmission rate on the basis of an amount of change of a travelling speed of at least either the transmitting device or the receiving device before and after the decrease in the transmission rate.

Abstract translation: 发送装置可以抑制视频质量的劣化并确定适当的传输速率，并且包括向接收装置发送通信分组的发送单元，接收作为与通信对应的响应信号的反馈分组的接收单元 从所述接收装置接收检测所述反馈分组的接收间隔的变化的检测部，以及传送速度决定部，其使所述发送部发送所述通信分组的传输速度降低， 检测接收间隔，并且基于传输速率降低之前和之后的发送设备或接收设备中的至少任一个的行进速度的改变量来增加传输速率。

公开(公告)号：US20120198264A1

公开(公告)日：2012-08-02

申请号：US13285131

申请日：2011-10-31

Applicant: Joseph T. DeMarco

Inventor： Joseph T. DeMarco

IPC: G06F1/12

CPC classification number: G06F1/10 ,  H03K5/135 ,  H04L7/0041 ,  H04L7/0337

Abstract: Primary serial interface logic is synchronized by cycling through a plurality of delays upon power up of the serial interface until a synchronization bit pattern is located. A minimum delay and a maximum delay are determined for the primary serial interface logic, and a delay is set to a midpoint between the minimum delay and the maximum delay. Secondary serial interface logic is synchronized by cycling through a plurality of delays until the output of the secondary serial interface logic equals the output of the primary serial interface logic. A minimum delay and a maximum delay are determined for the secondary serial interface logic, and a delay is set to a midpoint between the minimum delay and the maximum delay.

Abstract translation: 主串行接口逻辑通过在串行接口加电时循环多个延迟来同步，直到定位同步位模式。 对于主串行接口逻辑确定最小延迟和最大延迟，并且将延迟设置为最小延迟和最大延迟之间的中点。 次级串行接口逻辑通过循环多个延迟来同步，直到次级串行接口逻辑的输出等于主串行接口逻辑的输出。 对于次级串行接口逻辑确定最小延迟和最大延迟，并且将延迟设置为最小延迟和最大延迟之间的中点。

公开(公告)号：US07991097B2

公开(公告)日：2011-08-02

申请号：US11905797

申请日：2007-10-04

Applicant: Hui-Min Wang

Inventor： Hui-Min Wang

IPC: H04L7/00

CPC classification number: H04L7/0331 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0041

Abstract: A method for adjusting a serial data signal having multiple sets of bits includes the following steps. First, one set of bits in the serial data signal is over-sampled to generate a first set of over-sampled bits. Next, every adjacent two bits of the first set of over-sampled bits are compared to generate one set of edge bits. Then, a delay operation is determined according to the set of edge bits. Afterwards, a displacement operation is executed on next sets of bits in the serial data signal according to the delay operation.

Abstract translation: 一种用于调整具有多组位数的串行数据信号的方法包括以下步骤。 首先，串行数据信号中的一组位被过采样以产生第一组过采样位。 接下来，比较第一组过采样比特的每个相邻的两比特以产生一组边缘比特。 然后，根据边缘位的集合来确定延迟操作。 然后，根据延迟动作对串行数据信号中的下一组位执行位移动作。

公开(公告)号：US07965116B2

公开(公告)日：2011-06-21

申请号：US12591132

申请日：2009-11-10

Applicant: Masahiro Hatano ,  Masaru Kikuchi

Inventor： Masahiro Hatano ,  Masaru Kikuchi

IPC: H03L7/00

CPC classification number: H01L27/14609 ,  H03L7/0805 ,  H03L7/0995 ,  H03L7/183 ,  H04L7/0012 ,  H04L7/0041 ,  H04N5/225

Abstract: A timing adjustment circuit includes at least one data line; a phase synchronization circuit that includes a plurality of oscillation delay elements which oscillate an oscillation signal, and that is configured to oscillate the oscillation signal by synchronizing a phase of a feedback clock with a phase of a reference clock; at least one delay circuit that includes a delay element which is disposed on the data line and which is equivalent to one of the plurality of oscillation delay elements, and that is configured to delay data which is to be transmitted on the data line; and a delay adjustment unit configured to adjust an amount of delay of the delay element of the delay circuit in accordance with a signal associated with oscillation of the phase synchronization circuit.

公开(公告)号：US07711055B2

公开(公告)日：2010-05-04

申请号：US11387463

申请日：2006-03-23

Applicant: Boris Boskovic ,  Rostyslav Kyrychynskyi

Inventor： Boris Boskovic ,  Rostyslav Kyrychynskyi

IPC: H04B3/00

CPC classification number: G06F3/00 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0041 ,  H04L7/033

Abstract: A method and system are provided for aligning signals in a communication system. The method and system include alignment logic or functionality configured to compensate for signal propagation discrepancies when communicating signals between one or more other devices. The alignment logic may operate to adjust one or more communicated signals, so that signals that may have different propagation times arrive at one or more devices at a desired time. The system and method may be used when initializing a communication system and before communicating data. The system and method operate to adjust one or more signals, such as a data strobe signal in a memory system for example, so that the one or more signals arrive at one or more devices spaced apart in time within a defined tolerance at a desired time. The alignment logic is used to compensate for signal propagation delays which can be associated with a signal propagation path.

Abstract translation: 提供一种用于对准通信系统中的信号的方法和系统。 该方法和系统包括对准逻辑或功能，其被配置为在一个或多个其他设备之间传送信号时补偿信号传播差异。 对准逻辑可以操作以调整一个或多个传送的信号，使得可以具有不同传播时间的信号在期望的时间到达一个或多个设备。 在初始化通信系统和通信数据之前可以使用该系统和方法。 该系统和方法操作以调整一个或多个信号，例如存储器系统中的数据选通信号，使得一个或多个信号在期望的时间内在限定的公差内到达在时间上间隔开的一个或多个设备 。 对准逻辑用于补偿可能与信号传播路径相关联的信号传播延迟。

公开(公告)号：US20090274254A1

公开(公告)日：2009-11-05

申请号：US12305148

申请日：2007-06-11

Applicant: Kyoko Hirata

Inventor： Kyoko Hirata

IPC: H04L7/00

CPC classification number: H04L7/0091 ,  H03K19/00323 ,  H04L7/0041 ,  H04L25/028

Abstract: The logic block 103 generates a serial-data signal DATA using a clock signal CLK generated by a clock generator 104. Then, a skew adjusting unit 111 adjusts a delay of the serial-data signal DATA based on the phase relationship between the clock signal CLK and the serial-data signal DATA, and outputs resultant serial-data signal DATA-SK and clock signal CLK to a FF circuit 112. The FF circuit 112 shapes the serial-data signal DATA-SK using the clock signal CLK, and transmits the resultant serial-data signal DATA-FF to outside the device. Accordingly, even if jitter of a clock signal is superimposed on a data signal after signal processing, the influence of this jitter is reduced, thus providing a data transmitting device capable of transmitting a data signal to outside the device with the influence of the jitter reduced.

Abstract translation: 逻辑块103使用由时钟发生器104产生的时钟信号CLK来产生串行数据信号DATA。然后，偏斜调整单元111基于时钟信号CLK的相位关系来调整串行数据信号DATA的延迟 和串行数据信号DATA，并将合成的串行数据信号DATA-SK和时钟信号CLK输出到FF电路112.FF电路112使用时钟信号CLK对串行数据信号DATA-SK进行整形，并发送 得到串行数据信号DATA-FF到设备外部。 因此，即使信号处理后的时钟信号的抖动叠加在数据信号上，也能够减轻抖动的影响，提供能够以抖动减小的方式将数据信号发送到设备外部的数据发送装置 。