公开(公告)号：US20010011750A1

公开(公告)日：2001-08-09

申请号：US09752976

申请日：2000-12-28

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki ,  Takeshi Fukunaga

IPC分类号： H01L027/12 ,  H01L027/01 ,  H01L031/0392 ,  H01L027/148

CPC分类号： H01L29/78654 ,  H01L27/1203 ,  H01L29/78612

摘要： There is provided a semiconductor device having a new structure which allows a high reliability and a high field effect mobility to be realized in the same time. In an insulated gate transistor having an SOI structure utilizing a mono-crystal semiconductor thin film on an insulating layer, pinning regions are formed at edge portions of a channel forming region. The pinning regions suppress a depletion layer from spreading from the drain side and prevent a short-channel effect. In the same time, they also function as a path for drawing out minority carriers generated by impact ionization to the outside and prevent a substrate floating effect from occurring.

公开(公告)号：US20010004121A1

公开(公告)日：2001-06-21

申请号：US09739269

申请日：2000-12-19

发明人： Mitsunori Sakama ,  Noriko Ishimaru ,  Masahiko Miwa ,  Michinori Iwai

IPC分类号： H01L027/01 ,  H01L027/12 ,  H01L031/0392 ,  H01L021/00 ,  H01L021/84

CPC分类号： H01L27/12 ,  G02F1/13454 ,  H01L27/1248

摘要： To a provide a method of forming a layered film of a silicon nitride film and a silicon oxide film on a glass substrate in a short time without requiring a plurality of film deposition chambers. In a thin film transistor, a layered film including a silicon nitride oxide film (12) is formed between a semiconductor layer (13) and a substrate (11) using the same chamber. The silicon nitride oxide film has a continuously changing composition ration of nitrogen or oxygen. An electric characteristic of the TFT is thus improved.

摘要翻译： 为了提供在短时间内在玻璃基板上形成氮化硅膜和氧化硅膜的分层膜而不需要多个成膜室的方法。 在薄膜晶体管中，使用相同的室，在半导体层（13）和基板（11）之间形成包含氮氧化硅膜（12）的层状膜。 氮氧化硅膜具有连续变化的氮或氧的组成比。 因此TFT的电特性得到改善。

公开(公告)号：US20010002325A1

公开(公告)日：2001-05-31

申请号：US09746253

申请日：2000-12-21

发明人： Nobuhiko Oda ,  Shiro Nakanishi ,  Shinji Yuda ,  Tsutomu Yamada

IPC分类号： H01L031/0392 ,  H01L027/01 ,  H01L027/12 ,  H01L023/62 ,  H01L021/00 ,  H01L021/84 ,  H01L021/26 ,  H01L021/324 ,  H01L021/42 ,  H01L021/477

CPC分类号： H01L29/66765 ,  H01L29/78636

摘要： On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms. Furthermore, the film thickness T0 of the stopper is set in the range to fulfill the following expression: T0nullT1null(T2null8000 null)nullwhere T1 is the film thickness of the silicon oxide film and T2 is the film thickness of the silicon nitride film.

摘要翻译： 在配置有栅电极的透明基板上，淀积作为栅绝缘膜的氮化硅膜和氧化硅膜，形成作为有源区的半导体膜的多晶硅膜。 在对应于栅电极的多晶硅膜上，设置有阻挡层，并且沉积作为层间绝缘膜的氧化硅膜和氮化硅膜以覆盖该阻挡层。 挡块的膜厚度T0设定在800〜1200埃的范围内。 此外，止动器的膜厚度T0设定在满足以下表达式的范围内：<段落lvl =“0”>在线公式> T0 + T1 <=（T2×8000）½

公开(公告)号：US20010002324A1

公开(公告)日：2001-05-31

申请号：US09755679

申请日：2001-01-04

发明人： Masashi Maekawa ,  Yukihiko Nakata

IPC分类号： H01L021/00 ,  H01L021/84 ,  H01L027/01 ,  H01L027/12 ,  H01L031/0392 ,  C30B001/00 ,  H01L021/20 ,  H01L021/36

CPC分类号： H01L21/02672 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/2022 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/78675

摘要： A method has been provided to form a sheet of large grain crystallized silicon, in an early stage of transistor production, before the areas of the source and drain are defined. The method takes advantage of high annealing temperatures and transition metals to speed the lateral growth of silicide. By using higher temperatures, the number of amorphous enclaves is minimized and the transition metal nucleation site can be made small. A small transition metal nucleation site, in turn, can be more easily located near the center of a transistor, or where it is convenient. After annealing, the areas close to the silicide nucleation site are transformed into polycrystalline with a high electron mobility, desirable for the formation of source/drain and channel regions. Silicide products, away from the transistor active areas, are etched away when the area of the source and drain are defined. A product by process using the method of the above-described invention is also provided.

摘要翻译： 在源极和漏极的区域被限定之前，已经提供了在晶体管制造的早期阶段形成大晶粒结晶硅片的方法。 该方法利用高退火温度和过渡金属来加速硅化物的横向生长。 通过使用较高的温度，非晶层的数量被最小化，并且可以使过渡金属成核位置变小。 反过来，小的过渡金属成核位置可以更容易地位于晶体管的中心附近，或者在其方便的地方。 在退火之后，接近硅化物成核位置的区域被转化为具有高电子迁移率的多晶，对于形成源极/漏极和沟道区域是期望的。 当定义源极和漏极的区域时，远离晶体管有源区的硅化物产物被蚀刻掉。 还提供了使用上述发明的方法的方法的产品。

公开(公告)号：US20010002047A1

公开(公告)日：2001-05-31

申请号：US09761582

申请日：2001-01-18

申请人： Kabushiki Kaisha Toshiba

发明人： Mitsuaki Suzuki ,  Shinichi Kamagami ,  Takuji Nakazono

IPC分类号： H01L027/12 ,  H01L021/00 ,  H01L021/84

CPC分类号： H01L29/78696 ,  H01L29/66757 ,  H01L29/78609

摘要： A thin film transistor of this invention has a structure obtained by sequentially stacking, on an insulating substrate, a silicon nitride film, a silicon oxide film, a polysilicon thin film with a channel region and source and drain regions facing each other via the channel region, an insulating film, and a gate electrode. The boron concentration decreases from the channel region toward the silicon nitride film in the silicon oxide film region between the channel region and the silicon nitride film. The silicon oxide film region between the channel region and the silicon nitride film is made up of a first region which is in contact with the channel region and has a boron concentration of 1null1016 atoms/cm3 or more, and a second region between the first region and the silicon nitride film, which has a boron concentration of less than 1null1016 atoms/cm3. The first region has a thickness of 200 null or less.

摘要翻译： 本发明的薄膜晶体管具有以下结构：在绝缘基板上依次层叠氮化硅膜，氧化硅膜，具有沟道区域的多晶硅薄膜，以及经由沟道区域彼此相对的源极和漏极区域 ，绝缘膜和栅电极。 在沟道区域和氮化硅膜之间的氧化硅膜区域中，硼浓度从沟道区域朝向氮化硅膜减少。 沟道区域和氮化硅膜之间的氧化硅膜区域由与沟道区域接触并具有1×10 16原子/ cm 3以上的硼浓度的第一区域和第一区域之间的第二区域构成， 和硼浓度小于1×10 16原子/ cm 3的氮化硅膜。 第一区域的厚度为200埃以下。

公开(公告)号：US20040259327A1

公开(公告)日：2004-12-23

申请号：US10892454

申请日：2004-07-16

申请人： Shin-Etsu Handotai Co., Ltd.

发明人： Kiyoshi Mitani

IPC分类号： H01L021/30 ,  H01L021/46 ,  H01L027/01 ,  H01L029/207 ,  H01L029/227 ,  H01L027/12 ,  H01L029/167 ,  H01L031/0392 ,  H01L029/36

CPC分类号： H01L21/76256 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/84 ,  H01L27/1203

摘要： A silicon oxide film 3null, 3null is formed on each of the main surfaces of a first silicon single crystal substrate 1 (bond wafer) and a second silicon single crystal substrate 2 (base wafer), and the first and second silicon single crystal substrates are then brought into close contact so as to locate the silicon oxide films 3null, 3null in between in an atmosphere of a clean air supplied through a boron-releasable filter, to thereby produce an SOI wafer 10. The second silicon single crystal substrate 2 employed herein comprises a silicon single crystal substrate having a bulk resistivity of 100 nullnullcm or above. In thus produced SOI wafer 10, the silicon oxide film 3 has a depth profile of boron concentration in which the boron concentration reaches maximum at a thickness-wise position. This ensures manufacturing of SOI wafer excellent in high-frequency characteristics.

摘要翻译： 在第一硅单晶衬底1（接合晶片）和第二硅单晶衬底2（基底晶片）的每个主表面上形成氧化硅膜3'，3“，并且第一和第二硅单晶 然后使晶体基板紧密接触，以便在通过可硼剥离的过滤器供应的清洁空气的气氛中将氧化硅膜3'，3“定位在其间，从而产生SOI晶片10.第二硅 本申请使用的单晶基板2包含体积电阻率为100Ω·cm以上的硅单晶基板。 在这样制造的SOI晶片10中，氧化硅膜3具有在厚度方向上硼浓度达到最大的硼浓度的深度分布。 这确保制造高频特性优异的SOI晶片。

公开(公告)号：US20040197969A1

公开(公告)日：2004-10-07

申请号：US10406403

申请日：2003-04-03

发明人： Hao-Yu Chen ,  Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L021/84 ,  H01L021/00 ,  H01L031/062 ,  H01L027/12

CPC分类号： H01L29/78618 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78684

摘要： A device having a raised segment, and a manufacturing method for same. An SOI wafer is provided having a substrate, an insulating layer disposed over the substrate, and a layer of semiconductor material disposed over the insulating layer. The semiconductor material is patterned to form a mesa structure. The wafer is annealed to form a raised segment on the mesa structure.

摘要翻译： 具有凸起部分的装置及其制造方法。 提供SOI晶片，其具有衬底，设置在衬底上的绝缘层和设置在绝缘层上的半导体材料层。 图案化半导体材料以形成台面结构。 将晶片退火以在台面结构上形成凸起的段。

公开(公告)号：US20040099909A1

公开(公告)日：2004-05-27

申请号：US10601775

申请日：2003-06-24

发明人： Kyu Yeon Park ,  Ki Hoon Kim

IPC分类号： H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC分类号： B81B7/0006 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014

摘要： Disclosed is an MEMS device using an SOI wafer, the MEMS device comprising a first silicon layer, an insulation layer formed on the first insulation layer, a second silicon layer formed on the insulation layer, a protective layer formed on the second silicon layer, and a ground hole extending from an upper portion of the protective layer to the first silicon layer and having a conductive material therein, whereby a handle wafer in the MEMS device is connected to the ground hole without performing any additional wiring or bonding process.

摘要翻译： 公开了使用SOI晶片的MEMS器件，MEMS器件包括第一硅层，形成在第一绝缘层上的绝缘层，形成在绝缘层上的第二硅层，形成在第二硅层上的保护层，以及 从保护层的上部延伸到第一硅层并且在其中具有导电材料的接地孔，由此MEMS器件中的处理晶片连接到接地孔，而不执行任何额外的布线或接合工艺。

公开(公告)号：US20040075142A1

公开(公告)日：2004-04-22

申请号：US10600827

申请日：2003-06-23

发明人： Hideaki Matsuhashi

IPC分类号： H01L027/01 ,  H01L027/12

CPC分类号： H01L29/66772 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78654

摘要： A lower buried oxide film, a stress-relief film, an upper buried oxide film, and an SOI film are formed over a semiconductor substrate in this order. The thermal expansion coefficient of the stress-relief film is greater than the thermal expansion coefficient of the upper buried oxide film. The stress-relief film desirably has a thermal expansion coefficient equal to or greater than the thermal expansion coefficient of the SOI film. For example, it is formed of a silicon film, or of a composite film laminating a silicon film, a germanium film disposed thereon, and a silicon film disposed thereon. Accordingly, a semiconductor device having an SOI MOSFET is to be provided, which has excellent characteristics such as low parasitic capacitance and a small S value and is hardly affected by the stress generated by the difference between thermal expansion coefficients of the buried oxide film and the SOI film.

摘要翻译： 在半导体衬底上依次形成下埋氧化膜，应力缓和膜，上掩埋氧化膜和SOI膜。 应力缓释膜的热膨胀系数大于上部掩埋氧化膜的热膨胀系数。 应力消除膜理想地具有等于或大于SOI膜的热膨胀系数的热膨胀系数。 例如，其由硅膜或层叠硅膜的复合膜，配置在其上的锗膜和设置在其上的硅膜形成。 因此，提供具有SOI MOSFET的半导体器件，其具有优异的特性，例如低寄生电容和小的S值，并且几乎不受由掩埋氧化膜的热膨胀系数和 SOI膜。

公开(公告)号：US20040056309A1

公开(公告)日：2004-03-25

申请号：US10666865

申请日：2003-09-18

申请人： Samsung Electronics Co., Ltd.

发明人： Min-Su Kim

IPC分类号： H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L27/1203 ,  H01L21/76264 ,  H01L21/76895 ,  H01L21/84

摘要： A Silicon On Insulator (SOI) structure and method of producing an SOI structure that can prevent a short circuit between a Local Inter-Connect (LIC) and a well in the SOI structure is disclosed. The SOI structure includes a BOX layer of insulation material formed on a silicon substrate; an SOI layer formed on the BOX layer; a well formed within a device isolation area of the SOI layer such that its lower surface is in contact with the BOX layer; a field oxide film formed on a surface side within the well; a gate line formed across an active area on the SOI layer and a portion on the field oxide film; an Nnull type source/drain area formed within the active area along both sides of the gate line to contact its lower surface with the BOX layer; an insulation layer formed on such resultant structure; and an opening part that is formed within the insulation layer. The opening part can be opened in a Full Trench (FT) structure so that the active area is partially exposed, and can be opened in a Partial Trench (PT) structure on the field oxide film so that an upper part of the gate line of an adjacent transistor is exposed. An LIC fills in the opening part within the insulation layer, and in such construction, the SOI element is designed by an FT-LIC structure where the LIC is contacted with one portion of the active area of an optional transistor, and by a PT-LIC structure where the LIC is contacted with an upper part of the gate line on the field oxide film.

摘要翻译： 公开了一种可以防止SOI结构中的本地互连（LIC）和阱之间的短路的SOI结构的SOI绝缘体（SOI）结构和制造方法。 SOI结构包括形成在硅衬底上的绝缘材料BOX层; 形成在BOX层上的SOI层; 在SOI层的器件隔离区内良好地形成，使得其下表面与BOX层接触; 形成在井内的表面侧的场氧化膜; 形成在SOI层上的有源区和场氧化膜上的一部分上的栅极线; 在栅极线的两侧的有源区域内形成的N +型源极/漏极区域，以使其下表面与BOX层接触; 在这样的结构上形成的绝缘层; 以及形成在所述绝缘层内的开口部。 开口部分可以以全沟（FT）结构打开，使得有源区域部分暴露，并且可以在场氧化膜上以部分沟槽（PT）结构打开，使得栅极线的上部 暴露相邻晶体管。 LIC填充绝缘层中的开口部分，并且在这种结构中，SOI元件由FT-LIC结构设计，其中LIC与可选晶体管的有源区域的一部分接触，并且由PT- LIC结构，其中LIC与场氧化物膜上的栅极线的上部接触。