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公开(公告)号：US11653577B2
公开(公告)日：2023-05-16
申请号：US17112842
申请日：2020-12-04
申请人： STMicroelectronics (Crolles 2) SAS , Commissariat A L'Energie Atomique Et Aux Energies Alternatives
CPC分类号： H01L45/16 , H01L27/222 , H01L27/24 , H01L43/02 , H01L43/12 , H01L45/06 , H01L45/1233
摘要： A method for manufacturing an interconnection structure for an integrated circuit is provided. The integrated circuit includes a first insulating layer, a second insulating layer, and a third insulating layer. Electrical contacts pass through the first insulating layer, and a component having an electrical contact region is located in the second insulating layer. The method includes etching a first opening in the third layer, vertically aligned with the contact region. A fourth insulating layer is deposited to fill in the opening, and a second opening is etched to the contact region by passing through the opening in the third insulating layer. A metal level is formed by filling in the second opening with a metal.
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42.发明公开公开(公告)号：US20230144157A1
公开(公告)日：2023-05-11
申请号：US17520672
申请日：2021-11-07
CPC分类号： H01L43/12 , H01L27/222 , H01L43/02
摘要： Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first set of spacers are formed on the sidewalls of a bottom electrode. A reference layer is formed on the spacers and the bottom electrode. A second set of spacers are formed on the sidewalls of the first set of spacers and the reference layer. A tunnel barrier is formed on the reference layer and the second set of spacers. A free layer is formed on the tunnel barrier, where a width of the free layer is greater than a width of the reference layer. A metal hardmask is formed on the free layer. A third set of spacers are formed on the sidewalls of the metal hardmask, the free layer, the tunnel barrier, and the second set of spacers.
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公开(公告)号：US11646143B2
公开(公告)日：2023-05-09
申请号：US16418753
申请日：2019-05-21
发明人： Aakash Pushp
CPC分类号： H01F10/3259 , G11C11/161 , H01F10/3286 , H01F41/32 , H01L27/222 , H01L43/02 , H01L43/10 , H01L43/12
摘要： Various devices are described (along with methods for making them), where the device has a tunnel barrier sandwiched between two magnetic layers (one of the magnetic layers functioning as a free layer and the other of the magnetic layers functioning as a reference layer). One magnetic layer underlies the tunnel barrier and the other magnetic layer overlies the tunnel barrier, thereby permitting spin-polarized current to pass across the magnetic layers and through the tunnel barrier. At least one of the magnetic layers includes a metal oxide sublayer (e.g., an MgO sublayer) sandwiched between magnetic material.
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公开(公告)号：US20230139618A1
公开(公告)日：2023-05-04
申请号：US17862831
申请日：2022-07-12
发明人： Byoungjae BAE , Shin KWON , Jeongmin PARK , Manjin EOM , Hyungjong JEONG
摘要： A semiconductor device includes a substrate including a cell region and a peripheral region, interconnection lines on the cell region and the peripheral region, the interconnection lines being spaced apart from the substrate in a first direction perpendicular to a top surface of the substrate, a lower insulating layer on the cell region and the peripheral region, the lower insulating layer covering the interconnection lines, and a top surface of the lower insulating layer on the cell region being at a lower height than top surfaces of uppermost interconnection lines of the interconnection lines, and data storage patterns on the lower insulating layer on the cell region, the data storage patterns being horizontally spaced apart from each other, and the data storage patterns being connected directly to the top surfaces of the uppermost interconnection lines on the cell region.
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公开(公告)号：US20230138005A1
公开(公告)日：2023-05-04
申请号：US17589018
申请日：2022-01-31
发明人： Hsiang-Lun Kao , Chen-Chiu Huang , Chien-Hua Huang , Chung-Te Lin
摘要： An exemplary method includes forming a multilayer interlevel dielectric (ILD) layer having a metal-containing dielectric layer (e.g., an aluminum oxide layer) between a first dielectric layer and a second dielectric layer and forming a bottom electrode via in the multilayer ILD layer. The method further includes forming a bottom electrode layer over the bottom electrode via, magnetic tunnel junction (MTJ) layers over the bottom electrode layer, and a top electrode layer over the MTJ layers. The bottom electrode layer, the MTJ layers, and the top electrode layer are etched to form a bottom electrode, an MTJ element, and a top electrode, respectively, of a magnetoresistive random-access memory (MRAM). The etching, such as an ion beam etch, forms a recess in the multilayer ILD layer that extends to the metal-containing dielectric layer of the multilayer ILD layer. In some embodiments, the etching extends the recess into and/or through the metal-containing dielectric layer.
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公开(公告)号：US20230123764A1
公开(公告)日：2023-04-20
申请号：US17591141
申请日：2022-02-02
发明人： Nuo Xu , Yuan Hao Chang , Po-Sheng Lu , Zhiqiang Wu
摘要： An MRAM cell block and a magnetic shielding structure for the MRAM cell block are incorporated into a metal interconnect of an integrated circuit (IC) device. The magnetic shielding structure may be provided by metallization layers and via layers having wires and vias that incorporate a magnetic shielding material. The magnetic shielding material may form the wires and vias, form a liner around the wires, or may be a layer of the wires. The wires and vias may also include a metal that is more conductive than the magnetic shielding material. The metal interconnect may include layers above or below the magnetic shielding structure that lack the magnetic shielding material and are more conductive. The MRAM cell block with the magnetic shielding structure is optionally provided as a standalone memory device or incorporated into a 3-D IC device that includes a second substrate having a conventional metal interconnect.
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公开(公告)号：US11631807B2
公开(公告)日：2023-04-18
申请号：US17403753
申请日：2021-08-16
发明人： Kuk-Hwan Kim , Dafna Beery , Marcin Gajek , Michail Tzoufras , Kadriye Deniz Bozdag , Eric Ryan , Satoru Araki , Andy Walker
IPC分类号： H01L43/12 , H01L27/22 , H01L43/02 , H01L21/285 , H01L21/02 , H01L21/308 , H01L43/08 , H01L43/10 , H01L21/324
摘要： Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.
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公开(公告)号：US11631797B2
公开(公告)日：2023-04-18
申请号：US17095379
申请日：2020-11-11
IPC分类号： H01L39/22 , G11B5/31 , G11C11/16 , G11C11/44 , H01F10/32 , H01F41/32 , H01L27/22 , H01L39/02 , H01L39/12 , H01L39/24 , H01L43/02 , H01L43/10 , H01L43/12
摘要： A buffer layer can be used to smooth the surface roughness of a galvanic contact layer (e.g., of niobium) in an electronic device, the buffer layer being made of a stack of at least four (e.g., six) layers of a face-centered cubic (FCC) crystal structure material, such as copper, the at least four FCC material layers alternating with at least three layers of a body-centered cubic (BCC) crystal structure material, such as niobium, wherein each of the FCC material layers and BCC material layers is between about five and about ten angstroms thick. The buffer layer can provide the smoothing while still maintaining desirable transport properties of a device in which the buffer layer is used, such as a magnetic Josephson junction, and magnetics of an overlying magnetic layer in the device, thereby permitting for improved magnetic Josephson junctions (MJJs) and thus improved superconducting memory arrays and other devices.
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公开(公告)号：US20230100514A1
公开(公告)日：2023-03-30
申请号：US18045539
申请日：2022-10-11
摘要： Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
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公开(公告)号：US20230099303A1
公开(公告)日：2023-03-30
申请号：US17484649
申请日：2021-09-24
发明人： Dexin Kong , Ashim Dutta , Ekmini Anuja De Silva , Daniel Schmidt
摘要： A memory device is provided. The memory device includes a memory stack on a first dielectric layer, and a sidewall spacer on the memory stack. The memory device further includes a conductive cap on the sidewall spacer and the memory stack and an upper metal line on the conductive cap and the sidewall spacer, wherein the upper metal line wraps around the conductive cap, sidewall spacer, and memory stack.
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