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218 条记录 (耗时 0.02 秒)

    Clock synthesis for frequency scaling in programmable logic designs
    42.
    发明授权
    Clock synthesis for frequency scaling in programmable logic designs 有权

    公开(公告)号：US11177811B2

    公开(公告)日：2021-11-16

    申请号：US15719289

    申请日：2017-09-28

    申请人： Intel Corporation

    发明人： Michael D. Hutton ,  Audrey Kertesz

    IPC分类号： H03L7/08 ,  H03K5/135 ,  G06F30/34 ,  G06F30/331 ,  H03L7/22 ,  G06F30/396

    摘要： Systems and methods described herein are related to clock signal generation for synchronous electronic circuitry. Power management in electronic devices circuitry may be implemented by scaling the frequency multiple functional modules implemented in the synchronous electronic circuitry. The present disclosure discussed clock generators that may provide frequency scaling of clock signals for functional modules within an electronic device. Moreover, certain clock signal generators may reduce mitigate generation of large currents during frequency scaling by employing circuitry that leads to incremental frequency changes. Circuitry that allows substantially glitchless or reduced-glitch transition between clock rate frequencies are also discussed.

    Delay locked loop to cancel offset and memory device including the same
    47.
    发明授权
    Delay locked loop to cancel offset and memory device including the same 有权

    公开(公告)号：US10530371B2

    公开(公告)日：2020-01-07

    申请号：US16376444

    申请日：2019-04-05

    申请人： Samsung Electronics Co., Ltd.

    发明人： Juho Jeon ,  Hun-Dae Choi

    IPC分类号： H03L7/081 ,  G11C29/02 ,  H03L7/087 ,  H03L7/197 ,  H03L7/22 ,  G11C7/10 ,  G11C7/22 ,  H03L7/10

    摘要： A delay locked loop according to some example embodiments of the inventive concepts may include first, second, and third delay circuits, first and second phase detectors, and first and second controllers. The first delay circuit may generate a first clock by delaying a reference clock. The second and third delay circuits may be configured to generate a second and third clock respectively by delaying the first clock. The first and second phase detector may be configured to detect a phase difference between the second clock and the third clock and the third clock respectively. The first controller may be configured to adjust a delay of the third delay circuit using a detection result of the first phase detector. The second controller may be configured to adjust a delay of the first delay circuit using a detection result of the second phase detector.

    ELECTRONIC DEVICE INCLUDING PLURALITY OF PHASED LOCKED LOOP CIRCUITS
    48.
    发明申请
    ELECTRONIC DEVICE INCLUDING PLURALITY OF PHASED LOCKED LOOP CIRCUITS 审中-公开

    公开(公告)号：US20190379385A1

    公开(公告)日：2019-12-12

    申请号：US16434893

    申请日：2019-06-07

    申请人： Samsung Electronics Co., Ltd.

    发明人： Youngchang YOON ,  Kyuhwan AN ,  Daehyun KANG ,  Juho SON ,  Sunggi YANG ,  Donghyun LEE ,  Yunsung CHO

    IPC分类号： H03L7/183 ,  H03L7/22 ,  H03L7/197 ,  H03L7/07 ,  H04W72/04

    摘要： A communication technique for converging internet of everything (IoT) technology with a 5th generation (5G) communication system for supporting a higher data transfer rate beyond a 4G system is provided. The communication technique can be applied to intelligent services, based on 5G communication technology and IoT-related technology. In an embodiment, an electronic device includes a first processor configured to output a first signal for generating a first frequency signal, a second processor configured to output a second signal for generating a second frequency signal, a first radio frequency (RF) chip configured to output the first frequency signal, based on the first signal received from the first processor and a baseband signal, and a second RF chip configured to output the second frequency signal, based on the second signal received from the second processor and the first frequency signal outputted from the first RF chip.