公开(公告)号：US20210104602A1

公开(公告)日：2021-04-08

申请号：US17124124

申请日：2020-12-16

Applicant: United Microelectronics Corp.

Inventor： Wen-Shen Li ,  Ching-Yang Wen ,  Purakh Raj Verma ,  Xingxing Chen ,  Chee-Hau Ng

IPC: H01L29/06 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/306 ,  H01L21/311

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.

公开(公告)号：US10971676B2

公开(公告)日：2021-04-06

申请号：US16731064

申请日：2019-12-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Jian-Cheng Chen ,  Yu-Ping Wang ,  Yu-Ruei Chen

IPC: H01L27/22 ,  H01L43/02 ,  G11C11/16 ,  H01L27/02

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, wherein the ring of MTJ region comprises a first MTJ, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, each of the metal interconnect patterns includes a first metal interconnection connected to the first MTJ directly.

公开(公告)号：US10971610B2

公开(公告)日：2021-04-06

申请号：US16558329

申请日：2019-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Chun-Liang Hou ,  Wen-Jung Liao

IPC: H01L21/306 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a substrate; a buffer layer over the substrate, a GaN layer over the buffer layer, a first AlGaN layer over the GaN layer, a first AlN layer over the AlGaN layer, and a p-GaN layer over the first AlN layer.

公开(公告)号：US20210098623A1

公开(公告)日：2021-04-01

申请号：US17120243

申请日：2020-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/033 ,  H01L21/324 ,  H01L21/225 ,  H01L21/306 ,  H01L29/10

Abstract: A method of forming a semiconductor structure includes: providing a substrate including an upper surface, a gate structure disposed on the upper surface, a spacer disposed on a sidewall of the gate structure, a first region in the substrate, and a second region in the substrate; masking the second region and amorphizing the first region, such that an amorphous layer is formed in the first region; depositing a stress layer on the substrate, wherein the stress layer conformally covers the gate structure, the spacer, the first region and the second region; and recrystallizing the amorphous layer, thereby forming a dislocation in the first region.

公开(公告)号：US20210098342A1

公开(公告)日：2021-04-01

申请号：US17121696

申请日：2020-12-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Yu-Ruei Chen

IPC: H01L23/48 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a second gate structure, a first slot contact structure, a first gate contact structure, and a second gate contact structure. The substrate includes a first active region and a second active region elongated in a first direction respectively. The first gate structure, the second gate structure, and the first slot contact structure are continuously elongated in a second direction respectively. The first gate contact structure and the second gate contact structure are disposed at two opposite sides of the first slot contact structure in the first direction respectively.

公开(公告)号：US20210091069A1

公开(公告)日：2021-03-25

申请号：US17111220

申请日：2020-12-03

Applicant: United Microelectronics Corp.

Inventor： Ting-Yao Lin ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/74

Abstract: A semiconductor device of electrostatic discharge (ESD) protection is provided, including a deep N-type region, disposed in a substrate; a deep P-type region, disposed in the substrate; a first P-type well, disposed in the deep N-type region; a first N-type well, abutting to the first P-type well, disposed in the deep N-type region. Further, a second P-type well abutting to the first N-type well is disposed in the deep P-type region. A second N-type well abutting to the second P-type well is disposed in the deep P-type region. A side N-type well is disposed in the deep N-type region at an outer side of the first P-type well. A side P-type well is disposed in the deep P-type region at an outer side of the second N-type well.

公开(公告)号：US20210083084A1

公开(公告)日：2021-03-18

申请号：US16655252

申请日：2019-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Wen-Jung Liao

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer and a recess. The group III-V body layer is disposed on the substrate. The group III-V barrier layer is disposed on the group III-V body layer in the active region and the isolation region. The recess is disposed in the group III-V barrier layer in the active region.

公开(公告)号：US20210061643A1

公开(公告)日：2021-03-04

申请号：US17097175

申请日：2020-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Fan Hu ,  Chia-Wei Lee ,  Chang-Sheng Hsu ,  Weng-Yi Chen

IPC: B81B7/00 ,  G01N27/12 ,  B81B3/00

Abstract: A semiconductor sensor, comprising a gas-sensing device and an integrated circuit is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (IMD) layer formed above the substrate in the sensing area and in the interconnection area, and an interconnect structure formed in the interconnection area; further includes a sensing electrode, a second TiO2-patterned portion, and a second Pt-patterned portion on the second TiO2-patterned portion in the sensing area. The interconnect structure includes a tungsten layer buried in the IMD layer, wherein part of a top surface of the tungsten layer is exposed by at least a via. The interconnect structure further includes a platinum layer formed in said at least the via, a TiO2 layer formed on the IMD layer, a first TiO2-patterned portion and a first Pt-patterned portion.

公开(公告)号：US10935969B2

公开(公告)日：2021-03-02

申请号：US16285067

申请日：2019-02-25

Applicant: United Microelectronics Corp.

Inventor： Feng-Chi Chung ,  Ching-Hsing Hsieh ,  Yi-Chun Lin ,  Chien-Chuan Yu

IPC: G05B23/02 ,  G03F7/20

Abstract: A virtual metrology system at least includes a process apparatus including a set of process data, the process apparatus producing a workpiece according to the set of process data. A virtual metrology server is configured to gather the set of process data, cluster the set of process data to obtain data clusters, and compare the data clusters with patterns. If the data clusters meet the patterns corresponding to the data clusters, performing a corresponding maintenance, repair, and overhaul step on the process apparatus.

公开(公告)号：US20210057579A1

公开(公告)日：2021-02-25

申请号：US16572568

申请日：2019-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo-Shiun Chen ,  Chun-Jen Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Jhong-Yi Huang ,  Guan-Ying Wu

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/15 ,  H01L29/66 ,  H01L21/02

Abstract: A transistor with strained superlattices as source/drain regions includes a substrate. A gate structure is disposed on the substrate. Two superlattices are respectively disposed at two sides of the gate structure and embedded in the substrate. The superlattices are strained. Each of the superlattices is formed by a repeated alternating stacked structure including a first epitaxial silicon germanium and a second epitaxial silicon germanium. The superlattices serve as source/drain regions of the transistor.