公开(公告)号：US10088639B2

公开(公告)日：2018-10-02

申请号：US15195538

申请日：2016-06-28

Applicant: Mellanox Technologies, Ltd.

Inventor： Elad Mentovich ,  Itshak Kalifa ,  Sylvie Rockman ,  Alon Webman ,  Amir Prescher ,  Evelyn Landman ,  Anna Sandomirsky ,  Eitan Zahavi ,  Yaakov Gridish

IPC: G02B6/42 ,  G02B6/32 ,  G02B6/43

Abstract: An opto-mechanical coupler and corresponding method are provided. The coupler may include a first end and a second end configured to receive optical fibers and a top surface and bottomed surface defining a through hole extending between the top and bottom surfaces. The coupler may include a reflective surface that redirects the optical signals between a first direction and a second direction substantially perpendicular to the first direction. The coupler may position one or more optical fibers along a second direction such that an optical signal from the plurality of optoelectronic transceivers is directed into one or more optical fibers or an optical signal from the one or more optical fibers is directed into a plurality of the optoelectronic transceivers, with the coupler accommodating different diameters of optical fiber including POF, SMF, and/or MMF fiber.

公开(公告)号：US20180259723A1

公开(公告)日：2018-09-13

申请号：US15457265

申请日：2017-03-13

Applicant: Mellanox Technologies, Ltd.

Inventor： Elad Mentovich ,  Sylvie Rockman ,  Itshak Kalifa ,  Yaakov Gridish

IPC: G02B6/42 ,  H04B10/40 ,  G02B6/14 ,  G02B6/32

CPC classification number: G02B6/4206 ,  G02B6/14 ,  G02B6/32 ,  G02B6/4214 ,  G02B6/4292 ,  H04B10/40

Abstract: A optical assembly and a method of reducing interference using the same may be provided. The optical assembly may include an optical cable and an optical transceiver module. The optical transceiver module may include a socket configured to receive the optical cable, an electro-optical transducer configured to generate an optical signal, and an optical lantern. The optical lantern may include an optical prism that may receive the optical signal via a first surface, disperse the optical signal into a plurality of modes of the optical signal, and output the plurality of modes via a second surface. A mirror may reflect the optical signal from a first direction extending between the first surface and the mirror to a second direction extending between the mirror and the second surface. The optical lantern may direct at least one of the plurality of modes of the optical signal into the optical cable.

公开(公告)号：US10037299B1

公开(公告)日：2018-07-31

申请号：US15689160

申请日：2017-08-29

Applicant: Mellanox Technologies Ltd.

Inventor： Carl G. Ramey ,  Christopher D. Metcalf

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/4022

Abstract: A computing system comprises one or more core processors coupled to a communication network among the cores via a switch in each core and switching circuitry to forward data among cores and switches. Features include a programmable classification processor for directing packets, techniques for managing virtual functions on an IO accelerator card, packet scheduling techniques, multi-processor communication using shared FIFOs, programmable duty cycle adjustment and delay adjustment circuits, a new class of instructions that use a ready bit, and cache coherence and memory ordering techniques.

公开(公告)号：US10031857B2

公开(公告)日：2018-07-24

申请号：US14953462

申请日：2015-11-30

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Adi Menachem ,  Shlomo Raikin ,  Idan Burstein ,  Michael Kagan

IPC: G06F13/36 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/38 ,  G06F13/28

Abstract: A method in a system that includes first and second devices that communicate with one another over a fabric that operates in accordance with a fabric address space, and in which the second device accesses a local memory via a local connection and not over the fabric, includes sending from the first device to a translation agent (TA) a translation request that specifies an untranslated address in an address space according to which the first device operates, for directly accessing the local memory of the second device. A translation response that specifies a respective translated address in the fabric address space, which the first device is to use instead of the untranslated address is received by the first device. The local memory of the second device is directly accessed by the first device over the fabric by converting the untranslated address to the translated address.

公开(公告)号：US20180183895A1

公开(公告)日：2018-06-28

申请号：US15390558

申请日：2016-12-26

Applicant: Mellanox Technologies Ltd.

Inventor： Shahaf Shuler ,  Noam Bloch ,  Yossef Itigin

IPC: H04L29/08 ,  G06F9/54

CPC classification number: H04L67/32 ,  G06F9/546 ,  G06F2209/548

Abstract: A network adapter includes a network interface and circuitry. The network interface is assigned a single network address in a communication network, and is configured to receive, from one or more other nodes over the communication network, messages that are destined for processing by multiple threads in one or more processing cores of a network node including the network adapter, but are nevertheless addressed to the single network address. The circuitry is configured to hold a distribution rule for distributing the messages among multiple Receive Queues (RQs) that are accessible by the threads, and to select for each message received via the network interface a respective RQ, by applying the distribution rule to the message.

公开(公告)号：US09996498B2

公开(公告)日：2018-06-12

申请号：US14847021

申请日：2015-09-08

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Ariel Shahar ,  Maria Lubeznov

IPC: G06F15/167 ,  G06F15/173 ,  H04L29/08 ,  H04L12/861 ,  H04L12/933

CPC classification number: G06F15/17331 ,  H04L49/15 ,  H04L49/9068 ,  H04L67/1097

Abstract: Communication apparatus includes a host interface for connection, via a host bus, to a host processor and a host memory, which is mapped to an address space of the host bus, and a network interface, configured to transmit and receive packets over a network. A local memory is configured to hold data in a memory space that is not mapped to the address space of the host bus. Packet processing circuitry, which is connected between the host interface and the network interface and is connected to the local memory, is configured to receive from the network interface a packet carrying a remote direct memory access (RDMA) request that is directed to an address in the local memory, and to service the RDMA request by accessing the data in the local memory.

公开(公告)号：US20180156975A1

公开(公告)日：2018-06-07

申请号：US15368721

申请日：2016-12-05

Applicant: Mellanox Technologies, Ltd.

Inventor： Hen Seri ,  Andrey Ger ,  Samer Yasin

IPC: G02B6/255 ,  G02B6/44

CPC classification number: G02B6/2558 ,  G02B6/4471 ,  G02B6/4472

Abstract: A method for producing a fiberoptic fan-out includes creating a splice joint between a first fiberoptic cable and two or more second fiberoptic cables, such that at the splice joint, each of a plurality of first optical fibers in the first fiberoptic cable is spliced to a respective second optical fiber in one of the second fiberoptic cables. A tube slides over the cables to a position at which the splice joint is contained inside the tube. While the splice joint is contained inside the tube, the tube is filled with a fixative so as to fix the splice joint in the position.

公开(公告)号：US20180150741A1

公开(公告)日：2018-05-31

申请号：US15813181

申请日：2017-11-15

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan Levi ,  Tal Anker ,  Ohad Markus

IPC: G06N3/04 ,  G06N3/08

CPC classification number: G06N3/0454 ,  G06N3/0481 ,  G06N3/063 ,  G06N3/08 ,  G06T2207/20084

Abstract: Described embodiments include a system that includes one or more buffers and circuitry. The circuitry is configured to process a plurality of input values, by identifying each of the input values that is not zero-valued, and, for each value of the identified input values, computing respective products of coefficients of a kernel with the value and storing at least some of the respective products in the buffers. The circuitry is further configured to compute a plurality of output values, by retrieving respective sets of stored values from the buffers, at least some of the retrieved sets including one or more of the products, and summing the retrieved sets. The circuitry is further configured to output the computed output values. Other embodiments are also described.

公开(公告)号：US09983371B2

公开(公告)日：2018-05-29

申请号：US15064108

申请日：2016-03-08

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Morees Ghandour ,  Elad Mentovich ,  Itshak Kalifa ,  Sylvie Rockman ,  Dalit Kimhi ,  Alon Webman

IPC: G02B6/42 ,  G01J1/02 ,  G01J1/04 ,  H01S5/024 ,  H01S5/183

CPC classification number: G02B6/4271 ,  G01J1/0252 ,  G01J1/0425 ,  G02B6/4214 ,  G02B6/428 ,  G02B6/4292 ,  H01S5/02248 ,  H01S5/02415 ,  H01S5/183

Abstract: An apparatus and method of assembly are described that provide improved mechanisms for cooling an optoelectronic transducer in a fiber optic system. The apparatus includes a thermoelectric cooler (TEC) secured to the optoelectronic transducer for removing heat from the optoelectronic transducer in response to instructions from a TEC driver, as well as a microcontroller electrically connected to the TEC driver for monitoring temperature and communicating with the TEC driver to selectively activate and deactivate the TEC at least partially based on the monitored temperature and/or other measured/detected data to effect a more efficient cooling mechanism for optoelectronic transducers, such as VCSELs. In addition, the user may be able to configure the system to maintain the optoelectronic transducer within a user-defined range of temperatures. In this way, a longer life and better performance of the optoelectronic transducer may be achieved, and datacenter costs related to cooling and/or maintenance may be minimized.

公开(公告)号：US20180091125A1

公开(公告)日：2018-03-29

申请号：US15279002

申请日：2016-09-28

Applicant: Mellanox Technologies, Ltd.

Inventor： Andrew Carlson ,  Carl Ramey

IPC: H03K5/06 ,  H03K5/19 ,  G06F1/32

CPC classification number: H03K5/06 ,  G01R31/31725 ,  G06F1/3206 ,  G06F1/324 ,  H03K5/135 ,  H03K5/19

Abstract: An integrated circuit and method are described for compensating for voltage droop on an integrated circuit using a power supply voltage monitoring circuit and a high-resolution adaptive clock stretching circuit. In some example embodiments, the method includes monitoring power supply voltage on an integrated circuit, detecting a voltage droop such as a dynamic loss of power supply in the integrated circuit, and stretching a current clock cycle, according to the detected voltage droop, to provide more time for logic on the integrated circuit to complete before a next clock cycle.