公开(公告)号：US20200227451A1

公开(公告)日：2020-07-16

申请号：US16740050

申请日：2020-01-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent GAY ,  Frederic LALANNE ,  Yann HENRION ,  Francois GUYADER ,  Pascal FONTENEAU ,  Aurelien SEIGNARD

IPC: H01L27/146

Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.

公开(公告)号：US10707270B2

公开(公告)日：2020-07-07

申请号：US16357152

申请日：2019-03-18

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin ,  Simon Jeannot

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

公开(公告)号：US10705294B2

公开(公告)日：2020-07-07

申请号：US16295553

申请日：2019-03-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sylvain Guerber ,  Charles Baudot

IPC: G02B6/24 ,  G02B6/122 ,  G02B6/12 ,  G02B6/42

Abstract: An optical waveguide termination device includes a waveguide and metal vias surrounding an end portion of the waveguide. The end portion of the waveguide has a transverse cross-sectional area that decreases towards its distal end. The metal vias are orthogonal to a same plane, with the same plane being orthogonal to the transverse cross-section. The metal vias absorb light originating from the end portion when a light signal propagates through the waveguide, and the metal vias and the end portion provide that an effective index of an optical mode to be propagated through the waveguide progressively varies in the end portion. Additional metal vias may be present along the waveguide upstream of the end portion, with the additional metal vias bordering the waveguide upstream of the end portion providing that the effective index of an optical mode to be propagated through the waveguide varies progressively toward the end portion.

公开(公告)号：US20200150174A1

公开(公告)日：2020-05-14

申请号：US16680114

申请日：2019-11-11

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Manoj KUMAR ,  Lionel COURAU ,  GEETA ,  Olivier LE-BRIZ

IPC: G01R31/28 ,  H05K1/02 ,  H01L21/66 ,  H01L23/525

Abstract: An integrated circuit die has a peripheral edge and a seal ring extending along the peripheral edge and surrounding a functional integrated circuit area. A test logic circuit located within the functional integrated circuit area generates a serial input data signal for application to a first end of a sensing conductive wire line extending around the seal ring between the seal ring and the peripheral edge of the integrated circuit die. Propagation of the serial input data signal along the sensing conductive wire line produces a serial output data signal at a second end of the sensing conductive wire line. The test logic circuit compares data patterns of the serial input data signal and serial output data signal to detect damage at the peripheral edge of the integrated circuit die.

公开(公告)号：US10559611B2

公开(公告)日：2020-02-11

申请号：US16031710

申请日：2018-07-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Philippe Are

IPC: H01L27/146 ,  H01L27/148

Abstract: An image sensor includes a control circuit and pixels. Each pixel includes: a photosensitive area, a substantially rectangular storage area adjacent to the photosensitive area, and a read area. First and second insulated vertical electrodes electrically connected to each other are positioned opposite each other and delimit the storage area. The first electrode extends between the storage area and the photosensitive area. The second electrode includes a bent extension opposite a first end of the first electrode, with the storage area emerging onto the photosensitive area on the side of the first end. The control circuit operates to apply a first voltage to the first and second electrodes to perform a charge transfer, and a second voltage to block charge transfer.

公开(公告)号：US20200013820A1

公开(公告)日：2020-01-09

申请号：US16451918

申请日：2019-06-25

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Denis Rideau ,  Axel Crocherie

IPC: H01L27/146

Abstract: A multispectral image sensor includes a semiconductor layer and a number of pixels formed inside and on top of the semiconductor layer. Each pixel includes an active photosensitive area formed in a portion of the semiconductor layer laterally delimited by peripheral insulating walls. The pixels include a first pixel of a first type and a second pixel of a second type. The portion of semiconductor layer of the first pixel has a first lateral dimension selected to define a lateral cavity resonating at a first wavelength and the portion of semiconductor layer of the second pixel has a second lateral dimension different from the first lateral dimension. The second lateral dimension is selected to define a lateral cavity resonating at a second wavelength different from the first wavelength.

公开(公告)号：US10514749B2

公开(公告)日：2019-12-24

申请号：US15467614

申请日：2017-03-23

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Alps) SAS ,  STMicroelectronics SA

Inventor： Vincent Huard ,  Silvia Brini ,  Chittoor Parthasarathy

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3234 ,  G06F11/30 ,  G06F11/32 ,  G06F15/78 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296

Abstract: A system on a chip includes at least one integrated circuit that is configured to operate at least at one operating point. A monitoring circuit acquires at least the cumulative duration of activity of the at least one integrated circuit. An evaluation circuit establish at least one instantaneous state of aging of the at least one integrated circuit based on the at least one cumulative duration of activity. An adjustment circuit operates to change the at least one operating point on the basis of the at least one state of aging of the at least one integrated circuit.

公开(公告)号：US10511147B2

公开(公告)日：2019-12-17

申请号：US15992573

申请日：2018-05-30

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Thomas Ferrotti ,  Badhise Ben Bakir ,  Alain Chantre ,  Sebastien Cremer ,  Helene Duprez

IPC: H01S5/125 ,  H01S5/12 ,  H01S5/02 ,  H01S5/026 ,  H01S5/10 ,  H01S5/343 ,  H01S5/022 ,  H01S5/042 ,  H01S5/187 ,  H01S5/323 ,  G02B6/12 ,  G02B6/30 ,  G02B6/34

Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising: a III-V heterostructure gain medium (3); and an optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon. The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).

公开(公告)号：US20190341478A1

公开(公告)日：2019-11-07

申请号：US16398417

申请日：2019-04-30

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Hassan El Dirani ,  Pascal Fonteneau

IPC: H01L29/739 ,  H01L29/161 ,  H01L29/08

Abstract: A Z2-FET-type structure includes a first front gate, a second front gate, a first back gate doped with p-type dopants, and a second back gate doped with n-type dopants. The structure may also include a buried insulating layer between the front gates and the back gates, an anode region, a cathode region, and an intermediate region separating the anode region and the cathode region.

公开(公告)号：US10453919B2

公开(公告)日：2019-10-22

申请号：US15803959

申请日：2017-11-06

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal Chevalier ,  Alexis Gauthier

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/732 ,  H01L29/737

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.