公开(公告)号：US5877914A

公开(公告)日：1999-03-02

申请号：US782524

申请日：1997-01-10

Applicant: Walter S. Gontowski, Jr.

Inventor： Walter S. Gontowski, Jr.

IPC: G11B5/55 ,  G11B21/08 ,  H02P25/02 ,  H03F3/30 ,  G11B5/596 ,  H03F3/26

CPC classification number: G11B21/083 ,  H02P25/034 ,  H03F3/3071 ,  G11B5/5547

Abstract: An amplifier in which a clamping circuit is an integral part of the output stage structure is used as a voice coil driver for positioning the heads of a memory disk drive. The output stage, operating in class AB, comprises two bipolar transistors, the source and the sink transistors, serially connected between a power supply and a ground terminal, the serial connection between the emitter of the first transistor and the collector of the second transistor being the output terminal of the output stage. The base terminals of the two output transistors are connected to a bias circuit and to an input transistor, used as the signal control element. The clamping circuit is directly connected with the base terminals of the output transistors to limit the voltage on said base terminals between a first and a second voltage reference.

Abstract translation: 使用其中钳位电路是输出级结构的组成部分的放大器用作用于定位存储盘驱动器的磁头的音圈驱动器。 在AB类中工作的输出级包括串联连接在电源和接地端之间的两个双极晶体管，源极和漏极晶体管，第一晶体管的发射极和第二晶体管的集电极之间的串联连接为 输出级的输出端。 两个输出晶体管的基极端子连接到偏置电路和用作信号控制元件的输入晶体管。 钳位电路与输出晶体管的基极端子直接连接，以限制第一和第二参考电压之间的所述基极端子上的电压。

公开(公告)号：US5856696A

公开(公告)日：1999-01-05

申请号：US820406

申请日：1997-03-12

Applicant: Richard A. Blanchard

Inventor： Richard A. Blanchard

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/786 ,  H01L29/04

CPC classification number: H01L29/66651 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/0921 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78654

Abstract: A field-effect transistor structure is described having a monocrystalline silicon channel region which is epitaxially continuous with an underlying monocrystalline silicon body region. Polycrystalline silicon source and drain regions abut the channel region. The source and drain regions are electrically isolated from the underlying body region by a patterned dielectric layer, which may include a thick field oxide. A polycrystalline silicon gate is capacitively coupled with the channel region by a second dielectric layer. The gate may extend laterally to partly overlap the source and drain regions.

Abstract translation: 描述了具有与下面的单晶硅体区域外延连续的单晶硅沟道区的场效应晶体管结构。 多晶硅源极和漏极区域邻接沟道区域。 源极和漏极区域通过图案化的介电层与下面的主体区域电隔离，其可以包括厚场氧化物。 多晶硅栅极通过第二介电层与沟道区电容耦合。 栅极可以横向延伸以部分地重叠源极和漏极区域。

公开(公告)号：US5850139A

公开(公告)日：1998-12-15

申请号：US808455

申请日：1997-02-28

Applicant: William E. Edwards

Inventor： William E. Edwards

IPC: G05F3/26 ,  G05F1/56 ,  G05F1/565 ,  G05F1/575 ,  H03F3/343

CPC classification number: G05F1/575 ,  G05F1/565

Abstract: A voltage regulator with load pole stabilization is disclosed. An error amplifier has a non-inverting input receiving a reference voltage and an inverting input receiving a feedback voltage from the output of the voltage regulator. A gain stage has an input connected to the output of the error amplifier and an output connected to a pass transistor that provides current to a load. A variable impedance device such as a FET transistor configured as a variable resistor is connected between the input and output of the gain stage to provide variable zero to cancel the varying pole when the output current drawn by the load fluctuates. Consequently, the disclosed voltage regulator has high stability without a significant increase in power dissipation.

公开(公告)号：US5835427A

公开(公告)日：1998-11-10

申请号：US172854

申请日：1993-12-22

Applicant: David Charles McClure

Inventor： David Charles McClure

IPC: G11C29/50 ,  G11C7/00

CPC classification number: G11C29/50 ,  G11C11/41

Abstract: Accelerated failure of processing defects in an integrated circuit memory device is brought about by asserting all wordlines of the memory device to enable all passgates for a plurality of memory cells. Then all bitlines are pulled low to pull low all internal nodes of the plurality memory cells. All active devices in the memory device are turned off or limited to linear region operation. This allows a supervoltage to be applied to the wordlines with internal nodes of the memory cells held low by the bitlines, stressing an oxide barrier between memory cells and wordlines without damaging active devices due to the supervoltage.

Abstract translation: 集成电路存储器件中处理缺陷的加速故障是通过断言存储器件的所有字线来实现多个存储器单元的所有通过门。 然后将所有位线拉低以拉低多个存储器单元中的所有内部节点。 存储器件中的所有有源器件都被关闭或被限制在线性区域操作。 这允许将超电压施加到字线，其中由位线保持低电平的存储器单元的内部节点，强调存储器单元和字线之间的氧化物屏障，而不会由于超压而损坏有源器件。

公开(公告)号：US5834360A

公开(公告)日：1998-11-10

申请号：US690738

申请日：1996-07-31

Applicant: Mark R. Tesauro ,  Frank R. Bryant

Inventor： Mark R. Tesauro ,  Frank R. Bryant

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76216 ,  H01L21/7621

Abstract: A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the substrate surface; the masking layer preferably comprising a nitride layer overlying a pad oxide layer. The masking layer is patterned and etched to form openings exposing selected regions of the substrate surface. Recesses are formed into the substrate in the openings. Preferably a portion of the pad oxide layer is isotropically etched under the nitride layer forming an undercut region. An etch stop layer is formed over the substrate in the recesses filling in the undercut along the sidewalls. A second masking layer, preferably of nitride is formed over the etch stop layer and anisotropically etched to form nitride sidewalls in the openings. The etch stop layer may be etched away from the horizontal surfaces. The substrate in the openings is then oxidized to form a field oxide region substantially coplanar with the original substrate surface.

Abstract translation: 提供了一种用于在主体的半导体表面形成隔离结构的方法，以及由此形成的隔离结构。 在衬底表面的选定区域上形成掩模层; 掩模层优选地包括覆盖衬垫氧化物层的氮化物层。 对掩模层进行图案化和蚀刻以形成露出衬底表面的选定区域的开口。 凹口在开口中形成在基底中。 优选地，衬垫氧化物层的一部分在形成底切区域的氮化物层下被各向同性地蚀刻。 在沿着侧壁填充在底切中的凹部中的衬底上形成蚀刻停止层。 在蚀刻停止层上方形成优选氮化物的第二掩蔽层，并进行各向异性蚀刻以在开口中形成氮化物侧壁。 蚀刻停止层可以从水平表面被蚀刻掉。 然后将开口中的衬底氧化以形成与原始衬底表面基本上共面的场氧化物区域。

公开(公告)号：US5832596A

公开(公告)日：1998-11-10

申请号：US777635

申请日：1996-12-31

Applicant: Anthony Man-Chong Chiu

Inventor： Anthony Man-Chong Chiu

IPC: H01L21/60 ,  H01L23/08 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K3/36

CPC classification number: H01L23/49827 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/50 ,  H01L24/49 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48233 ,  H01L2224/49109 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19041

Abstract: A method for forming a package for an integrated circuit in which a plurality of conduction paths are formed on a first board and on a second board. Holes are formed in the first board and the second board wherein the holes are adapted for receiving pins. The holes are aligned and the first board is coupled to the second board using an adhesive.

Abstract translation: 一种用于形成集成电路的封装的方法，其中在第一板和第二板上形成多个导电路径。 孔形成在第一板和第二板中，其中孔适于接收销。 孔被对准，并且第一板使用粘合剂联接到第二板。

公开(公告)号：US5825691A

公开(公告)日：1998-10-20

申请号：US858788

申请日：1997-05-19

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C11/413 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C16/02 ,  G11C17/00 ,  G11C16/04

CPC classification number: G11C7/22 ,  G11C7/14

Abstract: A start write sensing circuit for sensing a start of a write is coupled to a write simulation circuit. The write simulation circuit preferably includes a memory cell replicate to mimic the amount of time required for writing data to the memory cell. The state of the data stored in the memory cell replicate is changed upon the write sensing circuit sensing the start of a write. The memory cell replicate is preferably constructed using the same structure, design, and process as the memory cells of the array so as to accurately simulate the time required for writing data to a memory cell in the array. Upon the write to the memory cell replicate being completed, a write termination signal is generated for terminating the write signal. The write termination signal also is a reset signal for resetting circuits of the array to prepare for the next cycle, whether it be a read or a write.

Abstract translation: 用于感测写入开始的开始写入感测电路耦合到写入模拟电路。 写入模拟电路优选地包括存储器单元复制以模拟将数据写入存储单元所需的时间量。 存储在存储单元复制中的数据的状态在写入感测电路感测写入的开始时被改变。 优选地，使用与阵列的存储器单元相同的结构，设计和处理来构造存储器单元复制，以便精确地模拟将数据写入阵列中的存储器单元所需的时间。 在完成对存储器单元复制的写入时，产生用于终止写入信号的写入终止信号。 写终止信号也是用于复位阵列的电路以准备下一个周期的复位信号，无论是读还是写。

公开(公告)号：US5825218A

公开(公告)日：1998-10-20

申请号：US736524

申请日：1996-10-24

Applicant: Gianluca Colli ,  Massimiliano Brambilla

Inventor： Gianluca Colli ,  Massimiliano Brambilla

IPC: H03K4/94 ,  H03K17/06 ,  H03K17/66 ,  H03K3/00

CPC classification number: H03K17/063 ,  H03K17/667 ,  H03K4/94

Abstract: A voltage ramp generator for a driver circuit is provided to give an output that is highly linear between zero and a maximum voltage has a combination of current sources or generators for charging and discharging a capacitor, with discharging performed by sequencing two different types of current sources. A first current source on the discharge side of the capacitor has transistors in cascode connected current mirrors and takes the capacitor voltage to a low value but not as low as zero. A second current source of a basic or simple current mirror then takes the capacitor voltage substantially to zero. The voltage ramp generator meets the requirements of high performance, integrated, driver circuits, particularly for achieving complete turn-off of a power device such as a DMOS transistor in a high side cascoded transistors goes up to a threshold near the full supply driver. It is optional to have two current sources for charging, also, where a first source with voltage and than a second source, in a basic current mirror, continues charging substantially to the supply voltage.

Abstract translation: 提供用于驱动器电路的电压斜坡发生器，以提供在零之间高度线性的输出，并且最大电压具有用于对电容器充电和放电的电流源或发生器的组合，通过对两种不同类型的电流源 。 在电容器的放电侧的第一电流源具有共源共栅电流镜中的晶体管，并将电容器电压降低到零，但不低于零。 基本或简单的电流镜的第二电流源然后将电容器电压基本上为零。 电压斜坡发生器满足高性能，集成的驱动器电路的要求，特别是为了实现功率器件的完全关断，例如在高侧的DMOS晶体管的共模感应晶体管在全电源驱动器附近达到阈值。 具有两个用于充电的电流源是可选的，而在基本电流镜中，具有电压和第二源的第一源也继续充电至电源电压。

公开(公告)号：US5808870A

公开(公告)日：1998-09-15

申请号：US720686

申请日：1996-10-02

Applicant: Anthony M. Chiu

Inventor： Anthony M. Chiu

IPC: H01L23/12 ,  H01L21/58 ,  H01L23/24 ,  H01L23/36 ,  H01L23/367 ,  H05K7/20

CPC classification number: H01L24/83 ,  H01L23/24 ,  H01L23/3675 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181

Abstract: A plastic pin support of a plastic PGA package is used to hold conductor pins in alignment, for electrical contact, with a printed circuit board and a socket. The printed circuit board is mounted on the plastic pin support which is electrically connected to respective conductor pins of the plastic pin support. A first adhesive layer, containing silver fillers, connects a silicon chip housed in the plastic PGA package to a heat sink and conducts heat from the silicon chip to the heat sink. The first adhesive layer also absorbs thermal expansion variations between the silicon chip and the heat sink during thermal cycles. A second adhesive layer connects the printed circuit board to the heat sink. Separation between the silicon chip and the printed circuit board is provided by a gap between the silicon chip and the printed circuit board which is filled with a protection layer, such as epoxy, to maintain separation between the silicon chip, the printed circuit board, and to protect the active surface of the silicon chip. The heat sink made of formable metal such as anodized Aluminum is formed around the silicon chip, the printed circuit board, and the plastic pin support providing heat dissipation and protection to the plastic pin support, the printed circuit board and the silicon chip.

Abstract translation: 塑料PGA封装的塑料针脚支撑用于将导体针与印刷电路板和插座对准，用于电接触。 印刷电路板安装在塑料销支撑件上，该塑料销支撑件电连接到塑料销支撑件的相应导体销。 包含银填料的第一粘合剂层将容纳在塑料PGA封装中的硅芯片连接到散热器，并将热量从硅芯片传导到散热器。 在热循环期间，第一粘合剂层还吸收硅芯片和散热器之间的热膨胀变化。 第二粘合剂层将印刷电路板连接到散热器。 硅芯片和印刷电路板之间的分离由硅芯片和填充有诸如环氧树脂等保护层的印刷电路板之间的间隙提供，以保持硅芯片，印刷电路板和 以保护硅芯片的有源表面。 由诸如阳极氧化铝的可成形金属制成的散热器形成在硅芯片，印刷电路板和塑料销支架周围，为塑料销支撑件，印刷电路板和硅芯片提供散热和保护。

公开(公告)号：US5804472A

公开(公告)日：1998-09-08

申请号：US644078

申请日：1996-05-09

Applicant: Artur P. Balasinski ,  Kuei-Wu Huang

Inventor： Artur P. Balasinski ,  Kuei-Wu Huang

IPC: H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/786 ,  H01L21/84

CPC classification number: H01L29/78696 ,  H01L27/11 ,  H01L27/1108

Abstract: The cross-sectional area of a thin-film transistor (TFT) is decreased in order to minimize bitline to supply leakage of the TFT. This is accomplished by utilizing a spacer etch process to manufacture a TFT having a very narrow and thin channel in a controllable manner. The spacer dimensions of the TFT may be adjusted by simply modifying the thicknesses of the poly gate and the channel poly. The channel thickness is limited by the thickness of the deposited channel polysilicon which may be as thin as approximately 300 .ANG. to 500 .ANG., and the channel width of the TFT corresponds to the height of the spacer etched along the polysilicon gate of the device which may be as small as approximately 0.15 to 0.25 .mu.m.

Abstract translation: 薄膜晶体管（TFT）的横截面面积减小，以便最小化位线以供应TFT的漏电。 这通过利用间隔物蚀刻工艺以可控的方式制造具有非常窄和窄的通道的TFT来实现。 可以通过简单地改变多晶硅栅和沟道多晶硅的厚度来调整TFT的间隔尺寸。 沟道厚度受到沉积沟道多晶硅厚度的限制，其厚度可以约为300埃至500埃，而TFT的沟道宽度对应于沿器件的多晶硅栅极蚀刻的间隔物的高度， 小至0.15〜0.25μm左右。