公开(公告)号：US11250901B2

公开(公告)日：2022-02-15

申请号：US17103374

申请日：2020-11-24

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C7/00 ,  G11C11/406 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02 ,  G06F1/3234 ,  G11C11/4074

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US11243897B2

公开(公告)日：2022-02-08

申请号：US16862916

申请日：2020-04-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Abhijit Abhyankar ,  Suresh Rajan

IPC: G06F13/16 ,  G06F11/20 ,  G06F13/00 ,  G06F13/42

Abstract: A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

公开(公告)号：US11226909B2

公开(公告)日：2022-01-18

申请号：US16546176

申请日：2019-08-20

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Frederick A. Ware ,  Brent S. Haukness

IPC: G06F3/00 ,  G06F13/16 ,  G06F3/06

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory device is disclosed. The memory device includes an array of storage cells and command interface circuitry to receive an internal transfer command. In response to the internal transfer command, transfer logic reads data from a first portion of the array of storage cells, transfers the data as on-chip transfer data, and writes the on-chip transfer data to a second portion of the array of storage cells. In response to the command interface circuitry receiving an interrupt command, the transfer logic pauses the internal transfer operation, and carries out an unrelated memory access operation involving at least the first portion of the array of storage cells or the second portion of the array of storage cells.

公开(公告)号：US20220005519A1

公开(公告)日：2022-01-06

申请号：US17376032

申请日：2021-07-14

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Brent Steven Haukness ,  Kenneth L. Wright ,  Thomas Vogelsang

IPC: G11C11/403 ,  G11C11/4097 ,  G11C11/4096 ,  G11C8/08 ,  G11C7/10 ,  G11C7/18 ,  G11C5/02 ,  G11C11/408 ,  G06F12/06 ,  G11C11/406 ,  G11C11/409

Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.

公开(公告)号：US11210242B2

公开(公告)日：2021-12-28

申请号：US16888551

申请日：2020-05-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright ,  John Eric Linstadt ,  Craig Hampel

IPC: G06F13/16 ,  G06F12/0868 ,  G06F12/0888 ,  G11C7/10 ,  G06F3/06 ,  G06F11/10 ,  G06F12/0895 ,  G06F13/28 ,  G11C29/52

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.

公开(公告)号：US20210383857A1

公开(公告)日：2021-12-09

申请号：US17334170

申请日：2021-05-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/408 ,  G11C5/04 ,  G11C11/4093 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

公开(公告)号：US11170842B2

公开(公告)日：2021-11-09

申请号：US16667844

申请日：2019-10-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C11/40 ,  G11C11/4093 ,  H01L25/065 ,  G11C5/04 ,  G11C11/4096 ,  G11C17/16 ,  G11C17/18 ,  H01L25/18 ,  H01L23/00

Abstract: A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.

公开(公告)号：US20210342231A1

公开(公告)日：2021-11-04

申请号：US17321053

申请日：2021-05-14

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Joseph James Tringali ,  Ely Tsern

IPC: G06F11/14 ,  G06F3/06 ,  G11C7/20 ,  G11C14/00

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

公开(公告)号：US20210335437A1

公开(公告)日：2021-10-28

申请号：US17245491

申请日：2021-04-30

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Frederick A. Ware ,  Suresh Rajan ,  Thomas Vogelsang

IPC: G11C29/24 ,  G06F11/10 ,  G11C29/50

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

公开(公告)号：US11133843B1

公开(公告)日：2021-09-28

申请号：US17074949

申请日：2020-10-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Carl W. Werner

IPC: H04B3/56 ,  H04L25/02 ,  H04B1/04 ,  H04B1/16

Abstract: An integrated-circuit output driver generates, in response to an input signal constrained to a first voltage range, a control signal at one of two voltage levels according to a data bit conveyed in the input signal, the two voltages levels defining upper and lower levels of a second voltage range substantially larger than the first voltage range. The output driver generates an output-drive signal constrained to a third voltage range according to the one of the two voltage levels of the control signal, the third voltage range being substantially smaller than the second voltage range.