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551.发明申请公开(公告)号：US20230050783A1
公开(公告)日：2023-02-16
申请号：US17861384
申请日：2022-07-11
Applicant: STMicroelectronics International N.V.
Inventor： Praveen Kumar VERMA , Harsh RAWAT
IPC: G11C11/419 , G11C11/418
Abstract: A memory array includes memory cells forming a data word location accessed in response to a word line signal. A data sensing circuit configured to sense data on bit lines associated with the memory cells. The sensed data corresponds to a current data word stored at the data word location. A data latching circuit latches the sensed data for the current data word from the data sensing circuit. A data modification circuit then performs a mathematical modify operation on the current data word to generate a modified data word. The modified data word is then applied by a data writing circuit to the bit lines for writing back to the memory cells of the memory array at the data word location. The operations are advantageously performed within a single clock cycle.
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公开(公告)号：US20230018420A1
公开(公告)日：2023-01-19
申请号：US17853026
申请日：2022-06-29
Applicant: STMicroelectronics International N.V.
Inventor： Praveen Kumar VERMA , Promod KUMAR , Harsh RAWAT
IPC: G11C8/20 , G11C11/418
Abstract: A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.
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公开(公告)号：US20220416768A1
公开(公告)日：2022-12-29
申请号：US17843780
申请日：2022-06-17
Applicant: STMicroelectronics International N.V.
Inventor： Kailash KUMAR , Manoj KUMAR
IPC: H03K3/012 , H03K3/3565
Abstract: An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a main PMOS branch that charges an intermediate node of the Schmitt trigger responsive to voltage transitions at the input node. The Schmitt trigger includes a charging assistance circuit that helps to rapidly charge the intermediate node of the Schmitt trigger. The charging assistance circuit includes a parallel PMOS branch in parallel with the main PMOS branch.
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公开(公告)号：US11522521B2
公开(公告)日：2022-12-06
申请号：US17223963
申请日：2021-04-06
Applicant: STMicroelectronics International N.V.
Inventor： Manoj Kumar Tiwari , Saiyid Mohammad Irshad Rizvi
Abstract: A glitch filter is provided. The glitch filter receives an input signal and sets a voltage level of an intermediary input node in accordance with a state of the input signal. The glitch filter charges or discharges a switched capacitance based on the voltage level of the intermediary input node and charges or discharges a filter capacitance based on a charge of the switched capacitance. The glitch filter sets a state of an output signal based on the charge of the filter capacitance. The glitch filter includes a reset stage that at least partially filters a burst of glitches in the input signal from the output signal by controlling the charge of the switched capacitance based on the state of the input signal and the state of the output signal.
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公开(公告)号：US11509323B2
公开(公告)日：2022-11-22
申请号：US17245592
申请日：2021-04-30
Applicant: STMicroelectronics International N.V.
Inventor： Anand Kumar , Ramji Gupta
IPC: H03M1/12
Abstract: A circuit includes an amplifier having first and second inputs and an output, and a feedback circuit configured to generate a feedback voltage in response to a voltage at the output of the amplifier. The feedback circuit is coupled to the first input of the amplifier to provide the feedback voltage to the first input of the amplifier. An output circuit is configured to generate a variable bias current in response to the voltage at the output of the amplifier. A switch circuit is configured to switch the second input of the amplifier from receiving a first reference voltage during a first mode of operation to receiving a second reference voltage during a second mode of operation.
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Patent Agency Ranking
公开(公告)号：US20220334862A1
公开(公告)日：2022-10-20
申请号：US17235206
申请日：2021-04-20
Inventor： Deepak BARANWAL , Amritanshu ANAND , Roberto COLOMBO , Boris VITTORELLI
Abstract: Disclosed herein is hardware for easing the process of changing the execution mode of a virtual machine and its associated resources. By adopting the hardware, it is possible to trigger a change in the execution mode in an automatic way, without software intervention, and without interfering with the execution of other virtual machines. In addition, in case an error has occurred for a virtual machine and it is detected, the hardware can be used to disable the resources associated with that virtual machine and generate notification of the completion this operation to other hardware, which will complete the reset of the virtual machine. By adopting the hardware, the execution mode change is simplified and offers configurability and flexibility for a system running multiple virtual machines.
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公开(公告)号：US11474788B2
公开(公告)日：2022-10-18
申请号：US16890870
申请日：2020-06-02
Inventor： Nitin Chawla , Tanmoy Roy , Anuj Grover , Giuseppe Desoli
Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.
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公开(公告)号：US20220320325A1
公开(公告)日：2022-10-06
申请号：US17705025
申请日：2022-03-25
Applicant: Exagan SAS , STMicroelectronics International N.V.
Inventor： Matthieu NONGAILLARD , Thomas OHEIX
IPC: H01L29/778 , H01L29/20
Abstract: The disclosure concerns an electronic device comprising a HEMT transistor, called main transistor, and at least another HEMT transistor, called additional transistor, stacked on each other. The main transistor and the additional transistor comprise a common drain electrode and, respectively, a main source electrode and an additional source electrode, arranged so that electric conduction paths likely to be formed by the two conduction layers are connected in parallel when one and the other of the HEMT transistors are in the conductive state.
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559.发明申请公开(公告)号：US20220319598A1
公开(公告)日：2022-10-06
申请号：US17697846
申请日：2022-03-17
Inventor： Roberto Bregoli , Vikas Rana
IPC: G11C16/04 , H01L27/11524 , H01L27/1156 , G11C16/10 , G11C16/14 , G11C16/26
Abstract: In an embodiment a non-volatile memory cell includes a substrate, a first body in the substrate, a second body in the substrate, a first storage transistor having a first conduction region and a second conduction region in the first body, the first and second conduction regions delimiting a first channel region in the first body, a first control gate region in the second body, an insulating region overlying the substrate, a single floating gate region extending on the substrate and embedded in the insulating region, the single floating gate region having a first portion on the first body and a second portion on the second body, the first portion and second portion being connected and electrically coupled, a first selection via extending through the insulating region and electrically coupling the first conduction region with a first conduction node, a second selection via extending through the insulating region and electrically coupling the second conduction region with a second conduction node and a first control via extending though the insulating region and electrically coupling the first control gate region with a first control node.
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560.发明授权公开(公告)号：US11451240B2
公开(公告)日：2022-09-20
申请号：US17344450
申请日：2021-06-10
Applicant: STMicroelectronics International N.V.
Inventor： Vivek Tripathi
Abstract: A quad signal generator circuit generates four 2N-1 bit control signals in response to a 2N-1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2N-1 unit DAC elements, with each unit DAC element including four switching circuits controlled by corresponding bits of the four 2N-1 bit control signals. Outputs of the 2N-1 unit DAC elements are summed to generate an analog output signal. The quad signal generator circuit controls a time delay applied to clock signals relative to the 2N-1 bit thermometer coded signal and a time delay applied to the 2N-1 bit thermometer coded signal relative to the delayed clock signals in logically generating the four 2N-1 bit control signals. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2N-1 bit thermometer coded signal.
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